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DRV8860PWPR Scheda tecnica(PDF) 31 Page - Texas Instruments |
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DRV8860PWPR Scheda tecnica(HTML) 31 Page - Texas Instruments |
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31 / 45 page ![]() VM OUT1 DIN CLK LATCH GND DOUT nFAULT ENABLE OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 10 µF 0.1 µF V3P3 DRV8860, DRV8860A www.ti.com SLRS065E – SEPTEMBER 2013 – REVISED NOVEMBER 2015 11 Layout 11.1 Layout Guidelines • The VM pin should be bypassed to GND using a low-ESR ceramic bypass capacitor with a recommended value of 0.1- μF rated for VM. • This capacitor should be placed as close as possible to the VM pin on the device with a thick trace or ground plane connection to the device GND pin. • The VM pin must be bypassed to ground using and appropriate bulk capacitor. This component must be located close to the DRV8860. 11.2 Layout Example Where the pull-up voltage (V3P3) is an external supply in the range of the recommended operating conditions for the digital open-drain outputs. Figure 39. DRV8860 Layout Copyright © 2013–2015, Texas Instruments Incorporated Submit Documentation Feedback 31 Product Folder Links: DRV8860 DRV8860A |
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