VNHD7012AYTR datasheet(30/43 Pages) STMICROELECTRONICS

30 / 43 page

VREG and Driver_LS Block

VNHD7012AY

30/43

DS11484 Rev 5

VREG and Driver_LS Block

VREG pin is the output of an internal low drop voltage regulator. VREG block is designed to

power the driver of external power Mosfet (Driver_LS) and it allows a proper MOS transition.



VREG out voltage will be VREG=10V if Vbattery > 10V, while VREG = Vbattery if

Vbattery < 10V.

An external capacitor CREG = 100 nF connected to the pin VREG is needed to proper

polarize the circuit (see Figure 16).

Reverse battery protection

CP pin provides the necessary gate drive for an external n-channel PowerMOS used for

reverse polarity protection. The external N-channel Power MOSFET used for the reverse

battery protection should have the following characteristics:



BVdss > 20 V (for a reverse battery of -16 V);



RDS(on) < 1/3 of H-bridge total RDS(on)



Standard Logic Gate Driving

Open-load detection in off-state

The Open Load (OL) detection in off-state operates when output is deactivated (means INA

= INB = PWM=0, or INB together with PWM=0). Open load detection is performed by

reading the MultiSense output. External (switched) pull-up resistor has to be used and

dimensioned to pull output voltage above the maximum open load detection voltage (VOL

MAX) when load is not connected and as well stays below the minimum level (VOL MIN)

when load is connected.

When the open load is detected, VsenseH is indicated on Multisense pin, possible

conditions are specified in Table 14.

If pull up resistor is applied over switched circuitry, it allows to detect short to VCC from

open-load (see Figure 16).

The RPU value has to be:

Rpull_up

VBATTmin VOLmax

–

2IL(off2)min [@VOLmax]



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