CY27EE16FZXECT datasheet(1/17 Pages) CYPRESS

Il numero della parte	CY27EE16FZXECT

Spiegazioni elettronici	1 PLL In-System Programmable Clock Generator with Individual 16K EEPROM

PDF	17 Pages

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Produttore elettronici	CYPRESS [Cypress Semiconductor]

Homepage	http://www.cypress.com

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1 / 17 page

1 PLL In-System Programmable Clock Generator

with Individual 16K EEPROM

CY27EE16ZE

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

, CA 95134

•

408-943-2600

Document #: 38-07440 Rev. *C

Revised December 21, 2004

Features

• 18 kbits of EEPROM

16 kbits independent scratch

2 kbits dedicated to clocking functions

• Integrated, phase-locked loop with programmable P

and Q counters, output dividers, and optional analog

VCXO, digital VCXO, spread spectrum for EMI reduction

• In system programmable through I2C Serial

Programming Interface (SPI). Both the SRAM and

non-volatile EEPROM memory bits are programmable

with the 3.3V supply

• Low-jitter, high-accuracy outputs

• VCXO with analog adjust

• 3.3V Operation (optional 2.5V outputs)

• 20-lead Exposed Pad, EP-TSSOP

Benefits

Higher level of integration and reduced component count by

combining EEPROM and PLL. Independent EEPROM may be

used for scratch memory, or to store up to eight clock config-

urations.

High-performance PLL enables control of output frequencies

that are customizable to support a wide range of applications.

Familiar industry standard eases programming effort and

enables update of data stored in 16K EEPROM scratchpad

and 2K EEPROM clock control block while CY27EE16ZE is

installed in system.

Meets critical timing requirements in complex system designs.

Write Protect (WP pin) can be programmed to serve as an

analog control voltage for a VCXO.The VCXO function is still

available with a DCXO, or digitally controlled (through SPI)

crystal oscillator if the pin is functioning as WP.

Meets industry-standard voltage platforms.

Industry standard packaging saves on board space.

Part Number

Outputs

Input Frequency Range

Output Frequency Range

CY27EE16ZE

6

1 – 167 MHz (Driven Clock Input) {Commercial}

1 –150 MHz (Driven Clock Input) {Industrial}

8 – 30 MHz (Crystal Reference) {Comm. or Ind.}

80 kHz – 200 MHz (3.3V) {Commercial}

80 kHz –167 MHz (3.3V) {Industrial}

80 kHz –167 MHz (2.5V) {Commercial}

80 kHz – 150 MHz (2.5V) {Industrial}

Logic Block Diagram

XIN

XOUT

CLOCK2

OUTPUT

DIVIDERS

PLL

OSC

CLOCK1

Q

VCO

VDD VSS

Φ

CLOCK3

P

Pin Configurations

SCL

SDAT

8x2k EEPROM

Memory Array

Clock

Configuration

Output

Crosspoint

Switch

Array

CLOCK5

CLOCK4

CLOCK6

[I2C- SPI:]

20-pin EP-TSSOP

AVDD AVSS

VDDL VSSL

CY27EE16ZE

PDM/OE

XIN 1

20 XOUT

VDD 2

19 VDD

CLOCK6 3

18 CLOCK5

AVDD 4

17 VCXO/WP

SDAT 5

16 VSS

AVSS 6

15 CLOCK4

VSSL 7

14 VDDL

CLOCK1 8

13 SCL

CLOCK2 9

12 CLOCK3

OE/PDM 10

11 VDDL

VCX/WP

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