CY27EE16ZE
Document #: 38-07440 Rev. *C
Page 14 of 17
AC Electrical Specifications (VDD = 3.3V)
Parameter[5]
Name
Description
Min.
Typ.
Max.
Unit
DC
Clock Output Duty Cycle
fOUT < 150 MHz
fOUT > 150 MHz, or fOUT = fREF
See Figure 8
45
40
50
50
55
60
%
ERO
Rising Edge Rate
Output Clock Edge Rate, Measured from 20%
to 80% of VDD, CLOAD = 15 pF See Figure 9.
0.8
1.4
V/ns
EFO
Falling Edge Rate
Output Clock Edge Rate, Measured from 80%
to 20% of VDD, CLOAD = 15 pF See Figure 9.
0.8
1.4
V/ns
t5
Output to Output Skew
For related clock outputs
250
ps
t9
Clock Jitter
Maximum absolute jitter (EEPROM quiet)
(during EEPROM reads)
(during EEPROM writes)
250
300
350
ps
t10
PLL Lock Time
60
ms
tVDDramp
Power Supply Ramp
Ramp time from 1.5V to 2.5V[6]
15
ms
tVDDpowerdown Power Supply Power Down
after Write
Wait time after a write to EEPROM is initiated
by the stop bit until VDD fails below 2.5V
20
ms
Memory Section Specifications
FSCL
SCL input frequency
400
kHz
tL
Clock Pulse Low
CLKLOW, 20–80% of VDD
1.2
µs
tH
Clock Pulse High
CLKHIGH, 80–20% of VDD
0.6
µs
tSP
Noise Suppression Time
Square noise spike on input
50
ns
tAA
Clock Low to Data Out Valid
0.1
0.9
µs
tBUFF
Time the bus must be free
before a new transmission
may start
1.2
µs
tHDSTART
Start Hold Time
0.6
µs
tSUSTART
Start Set-up Time
0.6
µs
tDH
Data in Hold Time
0
ms
tSU
Data in Set-up time
100
ns
tRI
Inputs rise time
300
ns
tFI
Inputs fall time
300
ns
tSUSTOP
Stop Set-up Time
0.6
µs
tDH
Data Out Hold Time
50
ns
tWR
Write Cycle Time
20
ms
Test and Measurement Set-up
Notes:
5. Not 100% tested.
6. The power supply voltage must increase monotonically from 0 to 2.5V; once VDD reaches 1.5V, it must ramp to 2.5V within 15 ms.
0.1
µF
VDD
CLK out
CLOAD
GND
OUTPUTS
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