CY27EE16FZXECT datasheet(11/17 Pages) CYPRESS

11 / 17 page

CY27EE16ZE

Document #: 38-07440 Rev. *C

Page 11 of 17

Sequential Read

Sequential read operations follow the same process as

random reads except that the master issues an acknowledge

instead of a STOP condition after transmission of the first 8-bit

data word. This action results in an incrementing of the internal

address pointer, and subsequently output of the next 8-bit data

word. By continuing to issue acknowledges instead of STOP

conditions, the master may serially read the entire contents of

the 16-kbit EEPROM scratchpad memory. When the internal

address pointer points to the FFH word of a EEPROM block,

after the next increment, the pointer will point to the 00H word

of the next block. After incrementing to the FFH word of the

eighth block, the next increment will point the pointer to the

00H word of the 1st EEPROM block. Similarly, sequential

reads within either the EEPROM or SRAM clock configuration

blocks will wrap within the block to the first word of the same

block after reaching the end of either block.

SCL

START

Condition

SDAT

STOP

Data may

Address or

Acknowledge

Valid

be changed

Condition

Figure 3. Data Transfer Sequence on the Serial Bus

SDAT Write

Start Signal

Device

Address

7-bit

R/W = 0

1 Bit

8-bit

Address

Slave

1 Bit

ACK

Slave

1 Bit

ACK

8-bit

Data

Stop Signal

Multiple

Contiguous

Registers

Slave

1 Bit

ACK

8-bit

Data

(XXH)

(XXH+1)

Slave

1 Bit

ACK

8-bit

Data

(XXH+2)

Slave

1 Bit

ACK

8-bit

Data

(XXH)

Slave

1 Bit

ACK

8-bit

Data

(X0H)

Slave

1 Bit

ACK

Slave

1 Bit

ACK

SDAT Read

Start Signal

Device

Address

7-bit

R/W = 1

1 Bit

8-bit

Data

Slave

1 Bit

ACK

Slave

1 Bit

ACK

Stop Signal

SDAT Read

Start Signal

Device

Address

7-bit

R/W = 0

1 Bit

8-bit

Address

Slave

1 Bit

ACK

Slave

1 Bit

ACK

7-bit

Device

Stop Signal

Multiple

Contiguous

Registers

Master

1 Bit

ACK

8-bit

Data

Master

1 Bit

ACK

(XXH)

Master

1 Bit

ACK

8-bit

Data

(XXH+1)

Master

1 Bit

ACK

8-bit

Data

(8FFH)

Master

1 Bit

ACK

8-bit

Data

(000H)

Master

1 Bit

ACK

Master

1 Bit

ACK

Current

Address

Read

16 byte wrap

Address

+R/W=1

Repeated

Start bit

Figure 4. Data Frame Architecture

SDAT

SCLK

Data Valid

Transition

to next Bit

CLKLOW

CLKHIGH

VIH

VIL

tSU

tDH

Figure 5. Data Valid and Data Transition Periods

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