AS7225 datasheet(39/76 Pages) AMSOSRAM

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AS7225

Datasheet

• PUBLIC

DS000496

• v2-00 • 2019-Jun-28

│ 38

Figure 37:

Director Channel_1 Result Register Low

Addr: 0x63

DIR_CH_1_L

Bit

Bit Name

Default

Access

Bit Description

7:0

DIR_CH_1_L

00000000

Channel 1 low byte

10.2.11

Director Channel_2 Result Registers (Addresses 0x64, 0x65)

These byte registers are used together as DIR_CH_2_H: DIR_CH_2_L

The registers create a 16-bit integer value from 0 to 65535 representing a PWM (Color + Dimming)

tuning percentage between 0.00 and 100.00%.

Example: 0001101001001111 = 1A4F = 6735 = 10.28%

Figure 38:

Director Channel_2 Result Register High

Addr: 0x64

DIR_CH_2_H

Bit

Bit Name

Default

Access

Bit Description

15:8

DIR_CH_2_H

00000000

Channel 2 high byte

CHAN_MODE 0 = Disabled

(0)

CHAN_MODE 1 = String1

COLOR_TUNING

CHAN_MODE 2 = String 2

COLOR_TUNING incl.

dimming

Figure 39:

Director Channel_2 Result Register Low

Addr: 0x65

DIR_CH_2_L

Bit

Bit Name

Default

Access

Bit Description

7:0

DIR_CH_2_L

00000000

Channel 2 low byte

10.2.12

Director Channel_3 Result Registers (Addresses 0x66, 0x67)

These byte registers are used together as DIR_CH_3_H: DIR_CH_3_L

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