R7KA8M2AFDCAM datasheet(8/295 Pages) RENESAS

8 / 295 page

1.2

Block Diagram

Figure 1.1 shows a block diagram of the MCU superset. Some individual devices within the group have a subset of the

features.

Memory

1 MB code

MRAM

2 MB SRAM

DMA

DMAC × 16

System

Mode control

Power control

protection

MOSC/SOSC

Clocks

(H/M/L) OCO

PLL1/PLL2

Battery backup

GPT32 x 14

Timers

ULPT × 2

RTC

CEU

Arm® Cortex®-M85

DTC × 2

CAC

POR/PVD

Reset

Human machine interfaces

ELC

Event link

RSIP-E50D

Security

Analog

CRC

Data processing

DOC

Communication interfaces

I3C

OSPI × 2

IIC × 3

SDHI × 2

SPI × 2

CANFD × 2

SSIE × 2

USBFS

SCI × 10

TSN

DAC12 × 2

ADC16H × 2

Bus

MPU

CSC

External

ICU × 2

ESWM

WDT × 2/IWDT

MPU

NVIC

System timer

Test and DBG

interface

IDAU

DSP

FPU

USBHS

AGT × 2

ACMPHS × 4

DOTF × 2

SDRAM

PDG x 4

PDMIF

Arm® Cortex®-M33

MPU

NVIC

System timer

Test and DBG

interface

IDAU

DSP

FPU

8 MB Flash

Note:

Not available on all part numbers.

Figure 1.1

Block diagram

1.3

Part Numbering

Figure 1.2 shows the product part number information, including memory capacity and package type. Table 1.13 shows a

list of products.

RA8M2 Datasheet

1. Overview

R01DS0438EJ0130 Rev.1.30

Feb 27, 2026

Page 8 of 295

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