R7KA8M2AFDCAM datasheet(18/295 Pages) RENESAS

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Table 1.15

Pin functions (6 of 7)

Function

Signal

I/O

Description

ESWM

ETn_GTX_CLK

Output 1000 Mb/s transmit clock

ETn_TX_CLK

Input

100 Mb/s,10 Mb/s transmit clock

ETn_RX_CLK

Input

Receive clock

ETn_TX_EN

Output Transmit enable

ETn_TXD0 to

ETn_TXD7

Output Transmit data

ETn_TX_ER

Output Transmit coding error

ETn_RX_DV

Input

Receive data valid

ETn_RXD0 to

ETn_RXD7

Input

Receive data

ETn_RX_ER

Input

Receive error

ETn_MDC

Output Management data clock

ETn_MDIO

I/O

Management data input/output

RGMIIn_TXC

Output Transmit clock

RGMIIn_RXC

Input

Receive clock

RGMIIn_TX_CTL

Output Transmit control

RGMIIn_TXD0 to

RGMIIn_TXD3

Output Transmit data

RGMIIn_RX_CTL

Input

Receive control

RGMIIn_RXD0 to

RGMIIn_RXD3

Input

Receive data

RMIIn_REF50CK

Input

Synchronous clock reference

RMIIn_TX_EN

Output Transmit enable

RMIIn_TXD0 to

RMIIn_TXD1

Output Transmit data

RMIIn_CRS_DV

Input

Carrier sense/Receive data valid

RMIIn_RXD0 to

RMIIn_RXD1

Input

Receive data

RMIIn_RX_ER

Input

Receive error

ETn_LINKSTA

Input

PHY Link Status

ETn_INT

Input

PHY interrupt

ETn_WOL

Output Wake-on-LAN. This signal indicates that a Magic Packet was received.

GPTP_CAPTUREn

Input

Media clock capture input

GPTP_MATCHn

Output Media clock recovery output

GPTP_PPSn

Output PPS signal

GPTP_PTPOUT0 to

GPTP_PTPOUT3

Output PTP Pulse generator signal

ET_TAS_STA0 to

ET_TAS_STA3

Output TAS status monitor

ETHPHYCLK

Output Clock output for PHY

PDMIF

PDMCLK0 to

PDMCLK2

Output Clock output pin

PDMDAT0 to

PDMDAT2

Input

Data input pin

RA8M2 Datasheet

1. Overview

R01DS0438EJ0130 Rev.1.30

Feb 27, 2026

Page 18 of 295

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