R7KA8M2AFDCAM datasheet(126/295 Pages) RENESAS

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Table 2.52

Timing of recovery from low power modes (3 of 3)

Parameter

Fast return

function*9

Symbol

Min

Typ

Max

Unit

Test

conditions

Recovery

time from

Deep

Software

Standby

mode

Deep Software

Standby mode

DPSBYCR.DC

SSMODE[1:0] =

—

tDSBY

—

296

346

µs

Figure 2.35

DPSBYCR.DC

SSMODE[1:0] =

—

456

506

µs

DPSBYCR.DC

SSMODE[1:0] =

—

776

826

µs

Deep Software

Standby mode

DPSBYCR.DC

SSMODE[1:0] =

—

296

346

µs

DPSBYCR.DC

SSMODE[1:0] =

—

456

506

µs

DPSBYCR.DC

SSMODE[1:0] =

—

776

826

µs

Deep Software

Standby mode

DPSBYCR.DC

SSMODE[1:0] =

—

483

604

µs

DPSBYCR.DC

SSMODE[1:0] =

—

643

764

µs

DPSBYCR.DC

SSMODE[1:0] =

—

963

1084

µs

Wait time after cancellation of Deep Software

Standby mode

—

tDSBYWT

22.2

—

33.6

µs

Note 1. When the frequency of the crystal is 48 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x05) and the

greatest value of the internal clock division setting is 1.

Note 2. When the frequency of PLL1P is 1 GHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x05) and the greatest

value of the internal clock division setting is 16.

Note 3. When the frequency of the external clock is 48 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x00) and

the greatest value of the internal clock division setting is 1.

Note 4. When the frequency of PLL1P is 1 GHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x00) and the greatest

value of the internal clock division setting is 16.

Note 5. The Sub-clock oscillator frequency is 32.768 kHz and the greatest value of the internal clock division setting is 1.

Note 6. The HOCO frequency is 20 MHz and the greatest value of the internal clock division setting is 1.

Note 7. The PLL frequency is 1 GHz and the greatest value of the internal clock division setting is 16.

Note 8. The MOCO frequency is 8 MHz and the greatest value of the internal clock division setting is 1.

Note 9. For details, see SSCR1.SS2FR bit.

Note 10. The recovery time can be calculated with the equation of tCommon + max(tOSCSTB, tPG1, tPGCK) + max(tPG2, tLPW). And they can be

determined with the following values and equations. For n, the greatest value is selected from among the internal clock(CPUCLK0,

CPUCLK1, NPUCLK, ICLK, MRICLK, MRPCLK, PCLKm, FCLK, BCLK and EBCLK) division settings (m = A to E).

tOSCSTB in the table below means the time when each oscillator is active. When multiple oscillators are active, tOSCSTB is

determined by the longest tOSCSTB among the active oscillators.

Note 11. The ICLK frequency is 250 MHz. This recovery time corresponds to tPG2.

Note 12. When Ccyc is 27. See Table 2.54.

RA8M2 Datasheet

2. Electrical Characteristics

R01DS0438EJ0130 Rev.1.30

Feb 27, 2026

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