R7KA8M2AFDCAM datasheet(241/295 Pages) RENESAS

241 / 295 page

Table 2.94

A/D conversion characteristics (SAR mode : External VDD mode) (6 of 6)

Conditions: AVCC: 2.7 to 3.63 V, VCC: 2.7 to 3.63 V, VREFH0/VREFH: 2.7 V to AVCC

Parameter

Min

Typ

Max

Unit

Test conditions

SAR

mode

Differential

input

High

accuracy

mode

High-speed

channels

(AN000 to

AN005)

(AN006 to

AN011)

Without

channel

dedicated

sample and

hold circuits

Conversion

time*1

0.26

—

µs

● ADCLK: 50 MHz

● Sampling time: 8 ADCLK

● Successive approximation time:

5 ADCLK

● Signal source impedance: 50 Ω

or less

Offset error

—

±1

±2.5

LSB

—

Full-scale

error

—

±1

±2.5

LSB

—

Absolute

accuracy

—

±2

±4

LSB

—

DNL

differential

nonlinearity

error *3

—

±0.75 ±1

LSB

—

INL integral

nonlinearity

error

—

±1.5

±2

LSB

—

High-speed

channels

(AN000 to

AN005)

(AN006 to

AN011)

With channel

dedicated

sample and

hold circuits

Conversion

time*2

1.72

—

µs

● ADCLK: 50 MHz

● Sampling time of channel-

dedicated sample-and-hold

circuits: 63 ADCLK

● Hold mode switching time of

channel-dedicated sample-and-

hold circuits: 2 ADCLK

●

Sampling time: 16 ADCLK

●

Successive approximation time:

5 ADCLK

● Signal source impedance: 50 Ω

or less

Offset error

—

±1.5

±6.75 LSB

—

Full-scale

error

—

±1.5

±6.75 LSB

—

Absolute

accuracy

—

±3.5

±9

LSB

—

DNL

differential

nonlinearity

error *3

—

±1

-1 to

+1.5

LSB

—

INL integral

nonlinearity

error

—

±2.5

±3.5

LSB

—

Note:

These specification values are applicable when only one ADC16H is operating, DAC12 and ACMPHS are not operating, and there

is no access to the external bus during A/D conversion.

If other ADC unit, DAC12, or ACMPHS is operating or bus access occurs during A/D conversion, values might not fall within the

indicated ranges.

The use of ports 0 as digital outputs is not allowed when the ADC16H is used.

The characteristics apply when AVCC0, AVSS0, VREFH0, VREFH, VREFL0, VREFL, and ADC16H input voltage is stable.

Note 1. Without channel dedicated sample and hold circuits; The conversion time is the sum of the sampling time and the successive

approximation time. Each of the above state is indicated for the test conditions.

Note 2. With channel-dedicated sample-and-hold circuits; The conversion time is the sum of the sampling time of channel-dedicated

sample-and-hold circuits, the hold mode switching time, the sampling time and the successive approximation time. Each of the

above state is indicated for the test conditions.

Note 3. DNL is measured using the Histogram Method, so the lower limit value is -1.

RA8M2 Datasheet

2. Electrical Characteristics

R01DS0438EJ0130 Rev.1.30

Feb 27, 2026

Page 241 of 295

R7KA8M2AFDCAM Scheda tecnica(PDF) 241 Page - Renesas Technology Corp

R7KA8M2AFDCAM Scheda tecnica(HTML) 241 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL