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Table 1.2

Memory (2 of 2)

Feature

Functional description

SRAM

On-chip high-speed SRAM with Error Correction Code (ECC).

OTP

On-chip OTP contains First Stage Bootloader (FSBL)

General purpose 96-byte OTP

Table 1.3

System

Feature

Functional description

Operating modes

Three operating modes:

● Single-chip mode

● JTAG boot mode

● SCI/USB boot mode

Resets

This MCU provides the following 21 types of reset.

Programmable Voltage Detection (PVD) The Programmable Voltage Detection (PVD) module monitors the voltage level input to the VCC

pin. The detection level can be selected by register settings. The PVD module consists of five

separate voltage level detectors (PVD0, PVD1, PVD2, PVD4, PVD5). These PVDs measure the

voltage level input to the VCC pin. PVD registers allow your application to configure detection of

VCC changes at various voltage thresholds.

Clocks

● Main clock oscillator (MOSC)

● Sub-clock oscillator (SOSC)

● High-speed on-chip oscillator (HOCO)

● Middle-speed on-chip oscillator (MOCO)

● Low-speed on-chip oscillator (LOCO)

● PLL1/PLL2

● Clock out support

Clock Frequency Accuracy

Measurement Circuit (CAC)

The Clock Frequency Accuracy Measurement Circuit (CAC) counts pulses of the clock to

be measured (measurement target clock) within the time generated by the clock selected

as the measurement reference (measurement reference clock), and determines the accuracy

depending on whether the number of pulses is within the allowable range. When measurement

is complete or the number of pulses within the time generated by the measurement reference

clock is not within the allowable range, an interrupt request is generated.

Interrupt Controller Unit (ICU)

The Interrupt Controller Unit (ICU) controls which event signals are linked to the Nested Vector

Interrupt Controller (NVIC), DMA Controller (DMAC) module and the Data Transfer Controller

(DTC) modules. The ICU also controls non-maskable interrupts.

Low power modes

Power consumption can be reduced in multiple ways, including setting clock dividers, controlling

EBCLK output, controlling SDCLK output, stopping modules, power gating control, selecting

operating power control modes in normal operation, and transitioning to low power modes and

processor low power modes.

Battery backup function

A battery backup function is provided for partial powering by a battery. The battery-powered

area includes the RTC, SOSC, backup register, tamper detection and VBATT_R voltage drop

detection and switch between VCC and VBATT.

The register write protection function protects important registers from being overwritten due to

software errors. The registers to be protected are set with the Protect Register (PRCR_S and

PRCR_NS).

Memory Protection Unit (MPU)

All bus masters have Memory Protection Units (MPUs).

Table 1.4

Event link

Feature

Functional description

Event Link Controller (ELC)

The Event Link Controller (ELC) uses the event requests generated by various peripheral

modules as source signals to connect them to different modules, allowing direct link between

the modules without CPU intervention.

Table 1.5

Direct memory access (1 of 2)

Feature

Functional description

Data Transfer Controller (DTC)

A Data Transfer Controller (DTC) module is provided for transferring data when activated by an

interrupt request.

RA8M2 Datasheet

1. Overview

R01DS0438EJ0130 Rev.1.30

Feb 27, 2026

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