R5F566TFCDFB datasheet(86/151 Pages) RENESAS

86 / 151 page

R01DS0315EJ0130 Rev.1.30

Page 86 of 151

Oct 06, 2023

RX66T Group

2. Electrical Characteristics

2.4.2

Clock Timing

Figure 2.4

BCLK Pin Output Timing

Table 2.18

BCLK Pin Output Clock Timing (1)

Conditions: 4.5 V ≤ VCC ≤ 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,

VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V,

Ta = Topr

Item

Symbol

Min.

Typ.

Max.

Unit

Test

Conditions

BCLK pin output cycle time

tBcyc

—

Figure 2.4

BCLK pin output high pulse width

tCH

7.5

—

BCLK pin output low pulse width

tCL

7.5

—

BCLK pin output rising time

tCr

——

BCLK pin output falling time

tCf

——

Table 2.19

BCLK Pin Output Clock Timing (2)

Conditions: 2.7 V ≤ VCC < 4.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,

VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V,

Ta = Topr

Item

Symbol

Min.

Typ.

Max.

Unit

Test

Conditions

BCLK pin output cycle time

tBcyc

31.25

—

Figure 2.4

BCLK pin output high pulse width

tCH

10.625

—

BCLK pin output low pulse width

tCL

10.625

—

BCLK pin output rising time

tCr

——

BCLK pin output falling time

tCf

——

tCf

tCH

tBcyc

tCr

tCL

BCLK pin output

Test conditions: VOH = 0.7 × VCC, VOL = 0.3 × VCC, C = 30 pF

High-drive output is selected by the driving ability control register.

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