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R5F566TFCDFB Scheda tecnica(PDF) 139 Page - Renesas Technology Corp

Il numero della parte R5F566TFCDFB
Spiegazioni elettronici  Renesas MCUs
PDF  151 Pages
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Produttore elettronici  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R5F566TFCDFB Scheda tecnica(HTML) 139 Page - Renesas Technology Corp

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R01DS0315EJ0130 Rev.1.30
Page 139 of 151
Oct 06, 2023
RX66T Group
2. Electrical Characteristics
Note 1. Definition of program/erase cycle:
The program/erase cycle is the number of erasing for each block. When the number of program/erase cycles is n, each block
can be erased n times. For instance, when 4-byte program is performed 512 times for different addresses in 2-Kbyte block and
then the block is erased, the program/erase cycle is counted as one. However, the same address cannot be programmed more
than once before the next erase cycle (overwriting is prohibited).
Note 2. Characteristics are degraded as the number of program/erase increases. This is the minimum value of program/erase cycles to
guarantee all characteristics listed in this table.
Note 3. This shows the characteristic when the flash memory writer or self-programming library from Renesas Electronics is in use, and
the number of times programming and erasure proceed does not exceed the specified value.
Note 4. These values are based on the results of reliability testing.
Table 2.57
Data Flash Memory Characteristics
Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,
VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V,
Temperature range for program/erase: Ta = Topr
Item
Symbol
FCLK = 4 MHz
20 MHz ≤ FCLK ≤ 60 MHz
Unit
Test Conditions
Min.
Typ.
Max.
Min.
Typ.
Max.
Program time
4 bytes
tDP4
—
0.36
3.8
—
0.16
1.7
ms
Erase time
64 bytes
tDE64
—3.1
18
—1.7
10
Blank check time
4 bytes
tDBC4
——
84
——
30
µs
64 bytes
tDBC64
—
—
280
—
—
100
2 Kbytes
tDBC2K
—
—
6160
—
—
2200
Program/erase cycles*1
NDPEC
100000
*2
—
—
100000
*2
—
—
Cycles
Program suspend latency
tDSPD
—
—
264
—
—
120
µs
Primary erase suspend latency in
suspend priority mode
tDSESD1
—
—
216
—
—
120
Secondary erase suspend latency in
suspend priority mode
tDSESD2
—
—
300
—
—
300
Erase suspend latency in erase
priority mode
tDSEED
—
—
300
—
—
300
Forced stop command
tFD
——
32
——
20
Data retention*3, *4
tDDRP
20
—
—
20
—
—
Year
Ta ≤ 85°C
10
—
—
10
—
—
Ta ≤ 105°C



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