R5F526TBAGFM datasheet(4/142 Pages) RENESAS

4 / 142 page

R01DS0407EJ0120 Rev.1.20

Page 4 of 142

Oct 31, 2024

RX26T Group

1. Overview

DMA

DMA controller

(DMACAa)

 8 channels

 Three transfer modes: Normal transfer, repeat transfer, and block transfer

 Request sources: Software trigger, external interrupts, and interrupt requests from

peripheral functions

Data transfer controller

(DTCb)

 Three transfer modes: Normal transfer, repeat transfer, and block transfer

 Request sources: External interrupts and interrupt requests from peripheral functions

I/O ports

Programmable I/O ports

 I/O ports for the 100-pin LFQFP

I/O pins: 82

Input pin: 1

Pull-up resistors: 82

Open-drain outputs: 82

5-V tolerance: 2

Large current output: 15

 I/O ports for the 80-pin LFQFP

I/O pins: 62

Input pin: 1

Pull-up resistors: 62

Open-drain outputs: 62

5-V tolerance: 2

Large current output: 14

 I/O ports for the 64-pin LFQFP, 64-pin HWQFN

I/O pins: 49

Input pin: 1

Pull-up resistors: 49

Open-drain outputs: 49

5-V tolerance: 2

Large current output: 14

 I/O ports for the 48-pin LFQFP, 48-pin HWQFN

I/O pins: 37

Input pin: 1

Pull-up resistors: 37

Open-drain outputs: 37

5-V tolerance: 2

Large current output: 13

 I/O ports for the 32-pin HWQFN

I/O pins: 21

Input pin: 1

Pull-up resistors: 21

Open-drain outputs: 21

5-V tolerance: 2

Large current output: 7

Event link controller (ELC)

 Event signals such as interrupt request signals can be interlinked with the operation of

functions such as timer counting, eliminating the need for intervention by the CPU to

control the functions.

 183 internal event signals can be freely combined for interlinked operation with

connected functions.

 Event signals from peripheral modules can be used to change the states of output pins

(of ports B and E).

 Changes in the states of pins (of ports B and E) being used as inputs can be interlinked

with the operation of peripheral modules.

Timers

8-bit timers (TMRb)

 (8 bits × 2 channels) × 4 units

 Select from among seven internal clock signals (PCLKB/1, PCLKB/2, PCLKB/8, PCLKB/

32, PCLKB/64, PCLKB/1024, PCLKB/8192) and one external clock signal

 Capable of output of pulse trains with desired duty cycles or of PWM signals

 The 2 channels of each unit can be cascaded to create a 16-bit timer

 Generation of triggers for A/D converter conversion

 Capable of generating baud-rate clocks for SCI5, SCI6, and SCI12

 Event linking by the ELC

Compare match timer

(CMT)

 (16 bits × 2 channels) × 2 units

 Select from among four internal clock signals (PCLKB/8, PCLKB/32, PCLKB/128,

PCLKB/512)

 Event linking by the ELC

Table 1.1

Outline of Specifications (3/9)

Classification

Module/Function

Description

R5F526TBAGFM Scheda tecnica(PDF) 4 Page - Renesas Technology Corp

R5F526TBAGFM Scheda tecnica(HTML) 4 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL