R5F526TBAGFM datasheet(6/142 Pages) RENESAS

6 / 142 page

R01DS0407EJ0120 Rev.1.20

Page 6 of 142

Oct 31, 2024

RX26T Group

1. Overview

Timers

General PWM timer

(GPTWa)

 32 bits × 8 channels (products with 64 Kbytes of RAM)

 16 bits × 8 channels (products with 48 Kbytes of RAM)

 Counting up or down (sawtooth-wave), counting up and down (triangle-wave) selectable

for all channels

 Clock sources independently selectable for each channel

 2 input/output pins per channel

 2 output compare/input capture registers per channel

 For the 2 output compare/input capture registers of each channel, 4 registers are

provided as buffer registers and are capable of operating as comparison registers when

buffering is not in use.

 In output compare operation, buffer switching can be at peaks or troughs, enabling the

generation of laterally asymmetrically PWM waveforms.

 Registers for setting up frame intervals on each channel (with capability for generating

interrupts on overflow or underflow)

 Generation of dead times in PWM operation

 Capable of synchronous start, stop, or clearing of counter for any channel

 Capable of a start, stop, clearing, or up-/down-counting of the counter supporting

maximum of 8 ELC events

 Capable of a start, stop, clearing, or up-/down-counting of the counter supporting input

level comparison

 Capable of a start, stop, clearing, or up-/down-counting of the counter supporting

maximum of 4 external triggers

 Output pin disabling function by a dead time error or a short circuit detection among

output pins

 Capable of generating conversion start triggers for the A/D converters as well as

monitoring external pins for a start timing of conversion.

 Capable of outputting events, such as compare-match from A to F and overflow/

underflow, to ELC

 Capable of using noise filter of input capture

 Periodic counting

 Internal peripheral bus clock: PCLKA

 Counter reference clock: PCLKC

 Frequency ratio: PCLKA to PCLKC = 1: N (N = 1 or 2)

High resolution PWM

(HRPWM)

 Capable of generating the PWM waveform that is generated by GPTW0 through GPTW3

with resolution of minimum of 260 ps.

Port output enable for

GPTW (POEG)

 Controlling the output disable for GPTW waveform output

 Initiation by input level detection of GTETRG pins

 Initiation by output disable request from GPTW

 Initiation by detection of comparator interrupt request

 Initiation by detection of oscillation stop or by software

Table 1.1

Outline of Specifications (5/9)

Classification

Module/Function

Description

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