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R5F526TBAGFM Scheda tecnica(PDF) 64 Page - Renesas Technology Corp |
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R5F526TBAGFM Scheda tecnica(HTML) 64 Page - Renesas Technology Corp |
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64 / 142 page ![]() R01DS0407EJ0120 Rev.1.20 Page 64 of 142 Oct 31, 2024 RX26T Group 2. Electrical Characteristics Note 1. Supply current values are measured when all output pins are unloaded and all input pull-up resistors are disabled. Note 2. Peripheral module clocks are supplied. This does not include operations as BGO (background operations). Note 3. ICC depends on f (ICLK) as follows. • D version product ICC Max. = 0.283 × f + 13 (full operation in normal operating mode) ICC Typ. = 0.107 × f + 4.3 (normal operation in normal operating mode) ICC Max. = 0.100 × f + 13 (sleep mode) • G version product ICC Max. = 0.285 × f + 17.8 (full operation in normal operating mode) ICC Typ. = 0.107 × f + 4.3 (normal operation in normal operating mode) ICC Max. = 0.093 × f + 17.8 (sleep mode) Note 4. This does not include operations as BGO (background operations). Whether the peripheral module clocks are supplied or stopped is controlled only by the bit settings in the module stop control registers A to D. Note 5. When peripheral module clocks are stopped, each clock frequency is set for division by 64, and the frequencies of FCLK, PCLKA, PCLKB, PCLKC, and PCLKD are the same. Note 6. This is an increase caused by program/erase operation to the code flash memory or data flash memory during executing the user program. Table 2.7 DC Characteristics (3) (Products with 48 Kbytes of RAM) Conditions: VCC = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5 V, VSS = AVSS0 = AVSS1 = AVSS2 = 0 V, Ta = Topr Item Symbol D version G version Unit Test Conditions Typ. Max. Typ. Max. Supply current*1 Full operation*2 ICC*3 — 47 — 52 mA ICLK = 120 MHz PCLKA = 120 MHz PCLKB = 60 MHz PCLKC = 120 MHz PCLKD = 60 MHz FCLK = 60 MHz Normal operation Peripheral module clocks are supplied*4 17 — 17 — Peripheral module clocks are stopped*4, *5 10 — 10 — CoreMark Peripheral module clocks are stopped*4, *5 16 — 16 — Sleep mode: Peripheral module clocks are supplied*4 13 25 13 29 All module clock stop mode (reference value) 7.4 16 7.4 20 Increase current by BGO operation*6 12 — 12 — Software standby mode 0.9 5 0.9 8 |
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