R8C datasheet(51/199 Pages) RENESAS

51 / 199 page

R8C/10 Group

Rev.1.20 Jan 27, 2006

page 41 of 180

REJ09B0019-0120

Figure 10.4 Time Required for Executing Interrupt Sequence

• Interrupt Sequence

An interrupt sequence — what are performed over a period from the instant an interrupt is accepted

to the instant the interrupt routine is executed — is described here.

If an interrupt occurs during execution of an instruction, the processor determines its priority when

the execution of the instruction is completed, and transfers control to the interrupt sequence from the

next cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA

instruction, the processor temporarily suspends the instruction being executed, and transfers control

to the interrupt sequence.

The CPU behavior during the interrupt sequence is described below. Figure 10.4 shows time re-

quired for executing the interrupt sequence.

(1) The CPU gets interrupt information (interrupt number and interrupt request priority level) by read-

ing the address 0000016. Then it clears the IR bit for the corresponding interrupt to “0” (interrupt

not requested).

(2) The FLG register immediately before entering the interrupt sequence is saved to the CPU internal

temporary register(1).

(3) The I, D and U flags in the FLG register become as follows:

The I flag is cleared to “0” (interrupts disabled).

The D flag is cleared to “0” (single-step interrupt disabled).

The U flag is cleared to “0” (ISP selected).

However, the U flag does not change state if an INT instruction for software interrupt numbers 32 to

63 is executed.

(4) The CPU’s internal temporary register(1) is saved to the stack.

(5) The PC is saved to the stack.

(6) The interrupt priority level of the accepted interrupt is set in the IPL.

(7) The start address of the relevant interrupt routine set in the interrupt vector is stored in the PC.

After the interrupt sequence is completed, the processor resumes executing instructions from the start

address of the interrupt routine.

NOTES:

1. This register cannot be used by user.

Indeterminate

SP-2

contents

SP-4

contents

VEC

contents

VEC+2

contents

Interrupt

information

Address

000016

Indeterminate

SP-2

SP-4

VEC

VEC+2

CPU clock

Address bus

Data bus

The indeterminate state depends on the instruction queue buffer. A read cycle occurs when the instruction queue buffer is ready

to accept instructions.

VEC+1

contents

SP-3

contents

SP-1

SP-3

VEC+1

SP-1

contents

10.1 Interrupt Overview

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