R8C datasheet(29/199 Pages) RENESAS

29 / 199 page

R8C/10 Group

Rev.1.20 Jan 27, 2006

page 19 of 180

REJ09B0019-0120

System clock control register 0(1)

SymbolAddressAfter reset

CM0000616

6816

Bit nameFunction

Bit symbol

b7b6b5b4b3b2b1b0

Set to “0”

CM05

(b3)

(b1-b0)

CM02

CM06

Reserved bit

WAIT peripheral function

clock stop bit

0 : Do not stop peripheral function clock in wait mode

1 : Stop peripheral function clock in wait mode

Reserved bit

Set to “1”

Reserved bit

Set to “0”

Main clock (XIN-XOUT)stop

bit(2, 4)

0 : On

1 : Off(3)

CPU clock division select

bit 0(5)

0 : CM16 and CM17 valid

1 : Divide-by-8 mode

Reserved bit

Set to “0”

NOTES:

1. Set the PRC0 bit of PRCR register to “1” (write enable) before writing to this register.

2. The CM05 bit is provided to stop the main clock when the on-chip oscillator mode is selected. This bit cannot be used for detection as to

whether the main clock stopped or not. To stop the main clock, the following setting is required:

(1) Set the OCD0 and OCD1 bits in the OCD register to “002” (disabling oscillation stop detection function).

(2) Set the OCD2 bit to “1” (selecting on-chip oscillator clock).

3. Set the CM05 bit to “1” (main clock stops) and the CM13 bit in the CM1 register to “1” (XIN-XOUT pin) when the external clock is input.

4. When the CM05 bit is set to “1” (main clock stop), P46 and P47 can be used as input ports.

5. When entering stop mode from high or middle speed mode, the CM06 bit is set to “1” (divide-by-8 mode).

000 0

(b4)

(b7)

Figure 6.2 CM0 Register and CM1 Register

6. Clock Generation Circuit

System clock control register 1(1)

SymbolAddressAfter reset

CM1000716

2016

Bit nameFunction

Bit symbol

CM10

All clock stop control bit(4)

0 : Clock on

1 : All clocks off (stop mode)

NOTES:

1. Write to this register after setting the PRC0 bit of PRCR register to “1” (write enable).

2. When entering stop mode from high or middle speed mode, the CM15 bit is set to “1” (drive capacity high).

3. Effective when the CM06 bit is “0” (CM16 and CM17 bits enable).

4. If the CM10 bit is “1” (stop mode), the internal feedback resistor becomes ineffective.

5. The CM14 bit can be set to “1” (on-chip oscillator off) if the OCD2 bit=0 (selecting main clock). When the OCD2 bit is set to “1”

(selecting on-chip oscillator clock), the CM14 bit is set to “0” (on-chip oscillator on). This bit remains unchanged when “1” is

written.

6. When the CM10 bit is set to “1” (stop mode) or the CM05 bit in the CM0 register to “1” (main clock stops) and the CM13 bit is set

to “1” (XIN-XOUT pin), the XOUT(P47) pin is held “H”.

When the CM13 bit is set to “0” (input port P46, P47), the P47 is in input state.

Reserved bit

Set to

“0”

CM15

XIN-XOUT drive capacity

select bit(2)

0 : LOW

1 : HIGH

CM16

CM17

Main clock division

select bit 1(3)

0 0 : No division mode

0 1 : Division by 2 mode

1 0 : Division by 4 mode

1 1 : Division by 16 mode

b7 b6

(b2)

Port XIN-XOUT switch bit

CM14

On-chip oscillation stop bit

0 : On-chip oscillator on

1 : On-chip oscillator off(5)

Reserved bit

Set to

“0”

(b1)

CM13

0 : Input port P46, P47

1 : XIN-XOUT pin

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