H8S2245 datasheet(89/818 Pages) RENESAS

Il numero della parte	H8S2245

Spiegazioni elettronici	Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series

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Section 2 CPU

Rev.3.00 Mar. 26, 2007 Page 47 of 772

REJ09B0355-0300

Table 2.9

System Control Instructions

Instruction

Size*

Function

TRAPA

—

Starts trap-instruction exception handling.

RTE

—

Returns from an exception-handling routine.

SLEEP

—

Causes a transition to a power-down state.

LDC

B/W

(EAs)

→ CCR, (EAs) → EXR

Moves the source operand contents or immediate data to CCR or EXR.

Although CCR and EXR are 8-bit registers, word-size transfers are

performed between them and memory. The upper 8 bits are valid.

STC

B/W

CCR

→ (EAd), EXR → (EAd)

Transfers CCR or EXR contents to a general register or memory.

Although CCR and EXR are 8-bit registers, word-size transfers are

performed between them and memory. The upper 8 bits are valid.

ANDC

CCR

∧ #IMM → CCR, EXR ∧ #IMM → EXR

Logically ANDs the CCR or EXR contents with immediate data.

ORC

CCR

∨ #IMM → CCR, EXR ∨ #IMM → EXR

Logically ORs the CCR or EXR contents with immediate data.

XORC

CCR

⊕ #IMM → CCR, EXR ⊕ #IMM → EXR

Logically exclusive-ORs the CCR or EXR contents with immediate data.

NOP

—

PC + 2

→ PC

Only increments the program counter.

Note:

Size refers to the operand size.

Byte

W: Word

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