H8S2245 datasheet(27/818 Pages) RENESAS

27 / 818 page

Rev.3.00 Mar. 26, 2007 Page xxvii of xlii

REJ09B0355-0300

Item

Page Revision (See Manual for Details)

Appendix B Register

Field

702

ADCSR H'FF98 A/D Converter

Note

*2 added

R/(W)

*1 DTC*2

Notes: 1. Can only be written with 0 for flag clearing.

2. DTC can clear this bit only when DISEL is 0 with the transfer

counter not being 0.

705

TCSR0 H'FFB2 8-Bit Timer Channel 0

TCSR1 H'FFB3 8-Bit Timer Channel 1

Note

*2 added

R/(W)

*1 DTC*2

Notes: 1. Can only be written with 0 for flag clearing.

2. DTC can clear this bit only when DISEL is 0 with the transfer

counter not being 0.

707

TCSR H'FFBC(W) H'FFBC(R) WDT

Note

*2 added

R/(W)

Overflow Flag

[Clearing condition] Cleared by reading TCSR

when OVF = 1, then writing 0 to OVF

Notes: The method for writing to ...

1. Can only be written with 0 for flag clearing.

2. When polling OVF with the interval timer interrupt disabled,

read TSCR twice or more while OVF is set to 1.

709

RSTCSR H'FFBE(W) H'FFBF(R) WDT

Figure amended

Watchdog Timer Overflow Flag [Clearing condition] Cleared by

reading RSTCSR when WOVF = 1, then writing 0 to WOVF

716

TSR0 H'FFD5 TPU0

Note

*2 added

R/(W)

*1 DTC*2

Notes: 1. Can only be written with 0 for flag clearing.

2. DTC can clear this bit only when DISEL is 0 with the transfer

counter not being 0.

H8S2245 Scheda tecnica(PDF) 27 Page - Renesas Technology Corp

H8S2245 Scheda tecnica(HTML) 27 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL