H8S2245 datasheet(25/818 Pages) RENESAS

25 / 818 page

Rev.3.00 Mar. 26, 2007 Page xxv of xlii

REJ09B0355-0300

Item

Page Revision (See Manual for Details)

Appendix B Register

Field

659

DTVECR H'FF37 DTC

Figure amended

SWDTE

R/(W)*1

DTVEC6

R/(W)*2

DTVEC5

R/(W)*2

DTVEC4

R/(W)*2

DTVEC3

R/(W)*2

DTVEC0

R/(W)*2

DTVEC2

R/(W)*2

DTVEC1

R/(W)*2

1. A value of 1 can always be written to the SWDTE bit, but 0 can only be written after 1

is read.

2. Only write to bits DTVEC6 to DTVEC0 when SWDTE is 0.

Notes:

DTC Software Activation Enable

Sets vector number for DTC software activation

Bit

Initial value

Read/Write

DTC software activation is disabled

[Clearing conditions]

• When the DISEL bit is 0 and the specified number of transfers have not ended

• When 0 is written to the DISEL bit after a software-activated data transfer end

interrupt (SWDTEND) request has been sent to the CPU.

DTC software activation is enabled

[Holding conditions]

• When the DISEL bit is 1 and data transfer has ended

• When the specified number of transfers have ended

• During data transfer activated by software

662

SCKCR H'FF3A Clock Pulse Generator

Figure amended

PSTOP

R/W

—

R/W

Bit

Initial value

Read/Write

680

SSR0 H'FF7C SCI0

Note

*2 added

R/(W)

*1 DTC*2

Notes: 1. Can only be written with 0 for flag clearing.

2. DTC can clear this bit only when DISEL is 0 with the transfer

counter not being 0.

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