HD6432147SW datasheet(34/1177 Pages) RENESAS

34 / 1177 page

Rev. 4.00 Sep 27, 2006 page xxxiv of xliv

14.1.2 Block Diagram ..................................................................................................... 408

14.1.3 Pin Configuration................................................................................................. 409

14.1.4 Register Configuration......................................................................................... 410

14.2

Register Descriptions ........................................................................................................ 410

14.2.1 Timer Counter (TCNT)........................................................................................ 410

14.2.2 Timer Control/Status Register (TCSR) ................................................................ 411

14.2.3 System Control Register (SYSCR) ...................................................................... 414

14.2.4 Notes on Register Access..................................................................................... 415

14.3

Operation .......................................................................................................................... 416

14.3.1 Watchdog Timer Operation ................................................................................. 416

14.3.2 Interval Timer Operation ..................................................................................... 417

14.3.3 Timing of Setting of Overflow Flag (OVF) ......................................................... 418

14.3.4

RESO Signal Output Timing ............................................................................... 419

14.4

Interrupts ........................................................................................................................... 419

14.5

Usage Notes ...................................................................................................................... 420

14.5.1 Contention between Timer Counter (TCNT) Write and Increment ..................... 420

14.5.2 Changing Value of CKS2 to CKS0...................................................................... 420

14.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode................ 421

14.5.4 System Reset by

RESO Signal............................................................................. 421

14.5.5 Counter Value in Transitions between High-Speed Mode, Subactive Mode,

and Watch Mode .................................................................................................. 421

14.5.6 OVF Flag Clear Condition ................................................................................... 422

Section 15 Serial Communication Interface (SCI, IrDA) ........................................ 423

15.1

Overview........................................................................................................................... 423

15.1.1 Features................................................................................................................ 423

15.1.2 Block Diagram ..................................................................................................... 425

15.1.3 Pin Configuration................................................................................................. 426

15.1.4 Register Configuration......................................................................................... 426

15.2

Register Descriptions ........................................................................................................ 428

15.2.1 Receive Shift Register (RSR) .............................................................................. 428

15.2.2 Receive Data Register (RDR) .............................................................................. 428

15.2.3 Transmit Shift Register (TSR) ............................................................................. 429

15.2.4 Transmit Data Register (TDR)............................................................................. 429

15.2.5 Serial Mode Register (SMR)................................................................................ 430

15.2.6 Serial Control Register (SCR).............................................................................. 433

15.2.7 Serial Status Register (SSR) ................................................................................ 436

15.2.8 Bit Rate Register (BRR) ...................................................................................... 441

15.2.9 Serial Interface Mode Register (SCMR).............................................................. 449

15.2.10 Module Stop Control Register (MSTPCR) .......................................................... 450

15.2.11 Keyboard Comparator Control Register (KBCOMP) .......................................... 452

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