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HD6432147SW Scheda tecnica(PDF) 98 Page - Renesas Technology Corp |
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HD6432147SW Scheda tecnica(HTML) 98 Page - Renesas Technology Corp |
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98 / 1177 page ![]() Section 2 CPU Rev. 4.00 Sep 27, 2006 page 54 of 1130 REJ09B0327-0400 Addressing Modes Function Instruction TRAPA ——— ——— ——— ——— — RTE ——— ——— ——— ——— — SLEEP ——— ——— ——— ——— — LDC B B W WWW — W — W —— —— STC — B W WWW — W — W —— —— ANDC, ORC, XORC B —— ——— ——— ——— —— System control NOP ——— ——— ——— ——— — Block data transfer ——— ——— ——— ——— — BW Legend: B: Byte W: Word L: Longword Notes: 1. Cannot be used in this LSI. 2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. 3. Only registers ER0 to ER6 should be used when using the STM/LDM instruction. |
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