HD6432147SW datasheet(40/1177 Pages) RENESAS

40 / 1177 page

Rev. 4.00 Sep 27, 2006 page xl of xliv

23.8.3 Error Protection.................................................................................................... 714

23.9

Interrupt Handling when Programming/Erasing Flash Memory....................................... 716

23.10 Flash Memory Programmer Mode .................................................................................... 717

23.10.1 Programmer Mode Setting ................................................................................... 717

23.10.2 Socket Adapters and Memory Map ..................................................................... 718

23.10.3 Programmer Mode Operation .............................................................................. 718

23.10.4 Memory Read Mode ............................................................................................ 719

23.10.5 Auto-Program Mode ............................................................................................ 723

23.10.6 Auto-Erase Mode ................................................................................................. 725

23.10.7 Status Read Mode ................................................................................................ 726

23.10.8 Status Polling ....................................................................................................... 727

23.10.9 Programmer Mode Transition Time .................................................................... 728

23.10.10 Notes on Memory Programming...................................................................... 729

23.11 Flash Memory Programming and Erasing Precautions ..................................................... 729

23.12 Note on Switching from F-ZTAT Version to Mask ROM Version .................................. 730

Section 24 Clock Pulse Generator .................................................................................. 731

24.1

Overview........................................................................................................................... 731

24.1.1 Block Diagram ..................................................................................................... 731

24.1.2 Register Configuration......................................................................................... 732

24.2

Register Descriptions ........................................................................................................ 732

24.2.1 Standby Control Register (SBYCR) .................................................................... 732

24.2.2 Low-Power Control Register (LPWRCR) ........................................................... 733

24.3

Oscillator........................................................................................................................... 734

24.3.1 Connecting a Crystal Resonator........................................................................... 734

24.3.2 External Clock Input ............................................................................................ 736

24.4

Duty Adjustment Circuit ................................................................................................... 739

24.5

Medium-Speed Clock Divider .......................................................................................... 739

24.6

Bus Master Clock Selection Circuit .................................................................................. 739

24.7

Subclock Input Circuit ...................................................................................................... 739

24.8

Subclock Waveform Shaping Circuit................................................................................ 740

24.9

Clock Selection Circuit ..................................................................................................... 741

Section 25 Power-Down State ......................................................................................... 743

25.1

Overview........................................................................................................................... 743

25.1.1 Register Configuration......................................................................................... 747

25.2

Register Descriptions ........................................................................................................ 747

25.2.1 Standby Control Register (SBYCR) .................................................................... 747

25.2.2 Low-Power Control Register (LPWRCR) ........................................................... 749

25.2.3 Timer Control/Status Register (TCSR) ................................................................ 751

25.2.4 Module Stop Control Register (MSTPCR) .......................................................... 752

HD6432147SW Scheda tecnica(PDF) 40 Page - Renesas Technology Corp

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