HD6432147SW datasheet(26/1177 Pages) RENESAS

26 / 1177 page

Rev. 4.00 Sep 27, 2006 page xxvi of xliv

2.8.5

Bus-Released State...............................................................................................

2.8.6

Power-Down State ...............................................................................................

2.9

Basic Timing .....................................................................................................................

2.9.1

Overview..............................................................................................................

2.9.2

On-Chip Memory (ROM, RAM) .........................................................................

2.9.3

On-Chip Supporting Module Access Timing ......................................................

2.9.4

External Address Space Access Timing ..............................................................

2.10

Usage Note........................................................................................................................

2.10.1 TAS Instruction....................................................................................................

2.10.2 STM/LDM Instruction .........................................................................................

Section 3 MCU Operating Modes .................................................................................. 83

3.1

Overview...........................................................................................................................

3.1.1

Operating Mode Selection ...................................................................................

3.1.2

3.2

Register Descriptions ........................................................................................................84

3.2.1

Mode Control Register (MDCR) .........................................................................

3.2.2

System Control Register (SYSCR) ......................................................................

3.2.3

Bus Control Register (BCR) ................................................................................

3.2.4

Serial Timer Control Register (STCR) ................................................................

3.3

Operating Mode Descriptions ...........................................................................................

3.3.1

Mode 1 .................................................................................................................

3.3.2

Mode 2 .................................................................................................................

3.3.3

Mode 3 .................................................................................................................

3.4

Pin Functions in Each Operating Mode ............................................................................

3.5

Memory Map in Each Operating Mode ............................................................................

Section 4 Exception Handling ......................................................................................... 103

4.1

Overview........................................................................................................................... 103

4.1.1

Exception Handling Types and Priority ............................................................... 103

4.1.2

Exception Handling Operation............................................................................. 104

4.1.3

Exception Sources and Vector Table ................................................................... 104

4.2

Reset.................................................................................................................................. 106

4.2.1

Overview.............................................................................................................. 106

4.2.2

Reset Sequence .................................................................................................... 106

4.2.3

Interrupts after Reset............................................................................................ 108

4.3

Interrupts ........................................................................................................................... 109

4.4

Trap Instruction................................................................................................................. 110

4.5

Stack Status after Exception Handling.............................................................................. 111

4.6

Notes on Use of the Stack ................................................................................................. 112

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