HD6432147SW datasheet(109/1177 Pages) RENESAS

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Section 2 CPU

Rev. 4.00 Sep 27, 2006 page 65 of 1130

REJ09B0327-0400

NOP, RTS, etc.

ADD.B Rn, Rm, etc.

MOV.B @(d:16, Rn), Rm, etc.

(1) Operation field only

(2) Operation field and register fields

(3) Operation field, register fields, and effective address extension

EA (disp)

(4) Operation field, effective address extension, and condition field

EA (disp)

BRA d:16, etc

Figure 2.12 Instruction Formats (Examples)

2.6.5

Notes on Use of Bit-Manipulation Instructions

The BSET, BCLR, BNOT, BST, and BIST instructions read a byte of data, carry out bit-

manipulation, then write back the byte of data. Caution is therefore required when using these

instructions on a register containing write-only bits, or a port.

The BCLR instruction can be used to clear internal I/O register flags to 0. In this case, the relevant

flag need not be read beforehand if it is clear that it has been set to 1 in an interrupt handling

routine, etc.

2.7

Addressing Modes and Effective Address Calculation

2.7.1

Addressing Mode

The CPU supports the eight addressing modes listed in table 2.4. Each instruction uses a subset of

these addressing modes. Arithmetic and logic instructions can use the register direct and

immediate modes. Data transfer instructions can use all addressing modes except program-counter

relative and memory indirect. Bit-manipulation instructions use register direct, register indirect, or

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