HD6432147SW datasheet(120/1177 Pages) RENESAS

Il numero della parte	HD6432147SW

Spiegazioni elettronici	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

PDF	1177 Pages

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Produttore elettronici	RENESAS [Renesas Technology Corp]

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Section 2 CPU

Rev. 4.00 Sep 27, 2006 page 76 of 1130

REJ09B0327-0400

Interrupt Exception Handling and Trap Instruction Exception Handling

When interrupt or trap-instruction exception handling begins, the CPU references the stack pointer

(ER7) and pushes the program counter and other control registers onto the stack. Next, the CPU

alters the settings of the interrupt mask bits in the control registers. Then the CPU fetches a start

address (vector) from the exception vector table and program execution starts from that start

address.

Figure 2.16 shows the stack after exception handling ends.

Note: * Ignored when returning.

CCR

(24 bits)

CCR

CCR*

(16 bits)

Normal mode

Advanced mode

Figure 2.16 Stack Structure after Exception Handling (Examples)

2.8.4

Program Execution State

In this state the CPU executes program instructions in sequence.

2.8.5

Bus-Released State

This is a state in which the bus has been released in response to a bus request from a bus master

other than the CPU. While the bus is released, all CPU internal operations are halted.

There is one other bus master in addition to the CPU: the data transfer controller (DTC).

For further details, refer to section 6, Bus Controller.

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