H8SX1663 datasheet(345/1158 Pages) RENESAS

Il numero della parte	H8SX1663

Spiegazioni elettronici	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

PDF	1158 Pages

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Produttore elettronici	RENESAS [Renesas Technology Corp]

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Section 6 Bus Controller (BSC)

Rev.1.00 Jun. 07, 2006 Page 293 of 1102

REJ09B0294-0100

(1) Consecutive Reads in Different Areas

If consecutive reads in different areas occur while bit IDLS1 in IDLCR is set to 1, idle cycles

specified by bits IDLCA1 and IDLCA0 when bit IDLSELn in IDLCR is cleared to 0, or bits

IDLCB1 and IDLCB0 when bit IDLSELn is set to 1 are inserted at the start of the second read

cycle (n = 0 to 7).

Figure 6.90 shows an example of the operation in this case. In this example, bus cycle A is a read

cycle for ROM with a long output floating time, and bus cycle B is a read cycle for SRAM, each

being located in a different area. In (a), an idle cycle is not inserted, and a conflict occurs in bus

cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted,

and a data conflict is prevented.

Data hold

time is long.

Data conflict

Bus cycle A

Bus cycle B

(a) No idle cycle inserted

(IDLS1 = 0)

(b) Idle cycle inserted

Address bus

CS (area A)

CS (area B)

Data bus

Bus cycle A

Bus cycle B

(IDLS1 = 1, IDLSELn = 0, IDLCA1 = 0, IDLCA0 = 0)

Figure 6.90 Example of Idle Cycle Operation (Consecutive Reads in Different Areas)

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