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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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H8SX1663 Scheda tecnica(PDF) 371 Page - Renesas Technology Corp |
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H8SX1663 Scheda tecnica(HTML) 371 Page - Renesas Technology Corp |
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371 / 1158 page  Section 7 DMA Controller (DMAC) Rev.1.00 Jun. 07, 2006 Page 319 of 1102 REJ09B0294-0100 A block diagram of the DMAC is shown in figure 7.1. External pins DREQn DACKn TENDn Interrupt signals requested to the CPU by each channel Internal activation sources Internal activation source detector Controller DMDR_n DMRSR_n DACR_n DOFR_n Internal address bus Internal data bus DSAR_n DDAR_n DTCR_n DBSR_n Module data bus Address buffer Data buffer Operation unit Operation unit ... [Legend] DSAR_n: DMA source address register DREQn: DMA transfer request DDAR_n: DMA destination address register DACKn: DMA transfer acknowledge DOFR_n: DMA offset register TENDn: DMA transfer end DTCR_n: DMA transfer count register n = 0 to 3 DBSR_n: DMA block size register DMDR_n: DMA mode control register DACR_n: DMA address control register DMRSR_n: DMA module request select register Figure 7.1 Block Diagram of DMAC |
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