H8SX1663 datasheet(367/1158 Pages) RENESAS

367 / 1158 page

Section 6 Bus Controller (BSC)

Rev.1.00 Jun. 07, 2006 Page 315 of 1102

REJ09B0294-0100

Also, since clock oscillation halts in software standby mode, if the

BREQ signal goes low in this

mode, indicating an external bus release request, the request cannot be answered until the chip has

recovered from the software standby mode.

Note that the

BACK and BREQO pins are both in the high-impedance state in software standby

mode.

(5) External Bus Release Function and CBR-Refresh or Auto-Refresh Cycle

The CBR refresh or auto-refresh cycle cannot be performed while the external bus is released.

When a CBR-refresh or an auto-refresh cycle is requested, the BREQO signal can be output by

setting the BREQOE bit in BCR1 to 1.

(6)

BREQO Output Timing

When the BREQOE bit is set to 1 and the

BREQO signal is output, both the BREQO and BACK

signals may go low simultaneously.

This will occur if the next external access request occurs while internal bus arbitration is in

progress after the chip samples a low level of the

BREQ signal.

(7) Refresh Settings

In single-chip activation mode, the setting of the RFSHE bit in REFCR should be made after

setting the EXPE bit in SYSCR to 1. For SYSCR, see section 3, MCU Operating Modes.

(8) Refresh Timer Settings

The setting of bits RTCK2 to RTCK0 in REFCR should be made after RTCNT and RTCOR have

been set. When changing RTCNT and RTCOR, the counter operation should be halted. When

changing bits RTCK2 to RTCK0, change them only after disabling external bus release and, if the

write data buffer function is in use, disabling the write data buffer function and reading the

external space.

H8SX1663 Scheda tecnica(PDF) 367 Page - Renesas Technology Corp