SH7101 datasheet(32/486 Pages) RENESAS

32 / 486 page

Rev.2.00 Sep. 27, 2007 Page xxxii of xxxiv

REJ09B0394-0200

Table 5.8

Interrupt Priority ........................................................................................................ 61

Table 5.9

Types of Exceptions Triggered by Instructions ......................................................... 62

Table 5.10

Generation of Exception Sources Immediately after Delayed Branch Instruction

or Interrupt-Disabled Instruction ............................................................................... 64

Table 5.11

Stack Status after Exception Processing Ends ........................................................... 65

Section 6 Interrupt Controller (INTC)

Table 6.1

Pin Configuration....................................................................................................... 68

Table 6.2

Interrupt Exception Processing Vectors and Priorities .............................................. 78

Table 6.3

Interrupt Response Time............................................................................................ 84

Section 7 Bus State Controller (BSC)

Table 7.1

Address Map .............................................................................................................. 88

Table 7.2

On-chip Peripheral I/O Register Access .................................................................... 90

Section 8 Multi-Function Timer Pulse Unit (MTU)

Table 8.1

MTU Functions.......................................................................................................... 92

Table 8.2

Pin configuration........................................................................................................ 95

Table 8.3

CCLR0 to CCLR2 (channels 0, 3, and 4) .................................................................. 99

Table 8.4

CCLR0 to CCLR2 (channels 1 and 2) ....................................................................... 99

Table 8.5

TPSC0 to TPSC2 (channel 0) .................................................................................. 100

Table 8.6

TPSC0 to TPSC2 (channel 1) .................................................................................. 100

Table 8.7

TPSC0 to TPSC2 (channel 2) .................................................................................. 101

Table 8.8

TPSC0 to TPSC2 (channels 3 and 4) ....................................................................... 101

Table 8.9

MD0 to MD3 ........................................................................................................... 103

Table 8.10

TIORH_0 (channel 0) .............................................................................................. 106

Table 8.11

TIORH_0 (channel 0) .............................................................................................. 107

Table 8.12

TIORL_0 (channel 0)............................................................................................... 108

Table 8.13

TIORL_0 (channel 0)............................................................................................... 109

Table 8.14

TIOR_1 (channel 1) ................................................................................................. 110

Table 8.15

TIOR_1 (channel 1) ................................................................................................. 111

Table 8.16

TIOR_2 (channel 2) ................................................................................................. 112

Table 8.17

TIOR_2 (channel 2) ................................................................................................. 113

Table 8.18

TIORH_3 (channel 3) .............................................................................................. 114

Table 8.19

TIORH_3 (channel 3) .............................................................................................. 115

Table 8.20

TIORL_3 (channel 3)............................................................................................... 116

Table 8.21

TIORL_3 (channel 3)............................................................................................... 117

Table 8.22

TIORH_4 (channel 4) .............................................................................................. 118

Table 8.23

TIORH_4 (channel 4) .............................................................................................. 119

Table 8.24

TIORL_4 (channel 4)............................................................................................... 120

Table 8.25

TIORL_4 (channel 4)............................................................................................... 121

Table 8.26

Output Level Select Function .................................................................................. 131

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