THMC50

REMOTE/LOCAL TEMPERATURE MONITOR AND

FAN CONTROLLER WITH SMBus INTERFACE

SLIS090 – JULY 1999

11

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

Table 1. THMC50 ADD Terminal States and Resulting SMBus Slave Address

ADD TERMINAL

RESULTING THMC50 SMBUS ADDRESS

GND

0101110

No Connect

0101100

VCC

0101101

Refer to Figure 1 through Figure 5 for the SMBus timing diagrams. The THMC50 does not support the SMBSUS

or SMBALERT sideband signals referenced in the SMBus specification.

THMC50 usage

The following sections describe the typical usage for the THMC50.

power-on reset

Applying power to the VCC3AUX terminal causes a reset of all of the registers to their default states. Some

registers have indeterminate power-on values, such as the limit and RAM registers, and these are not shown

in the table. Writing limit values into the value RAM should be the first action performed after power up. Refer

to the register definition tables for default power-on values of all other registers.

If the FAN_SPD/NTEST_IN terminal is held high during power-on reset, the THMC50 enters the NAND tree test

mode. Once the NAND tree test mode is enabled, it can only be disabled by cycling VCC3AUX power.

The FAN_SPD analog output is reset to 0x00 whenever RST is asserted low. During the time RST is asserted

low, a THERM assertion will still cause the FAN_SPD analog output to go to full scale (0xFF).

The THMC50 contains a bidirectional reset terminal, AUXRST, which causes an internal reset when pulled low

externally. Refer to the section describing AUXRST for more detail.

soft reset

The THMC50 can be commanded to perform an internal soft reset by setting bit 4 of the configuration register

(0x40). This bit automatically clears itself after being set. A soft reset performs a similar reset to the power-on

reset, except that the value RAM remains unchanged. Registers that are reset by both types of reset include:

0

×40 configuration register

0

×41 interrupt status register

0

×43 interrupt mask register

0

×4C interrupt status register mirror

beginning a conversion

The THMC50 monitoring function is started by default. It is expected that the system BIOS initializes the

THMC50 as quickly as possible during POST. The BIOS should then clear the INT clear (bit 2) and set INT

enable (bit 1) in the configuration register (0

×40) in order to enable THMC50 interrupts and the INT function.

The results of the sampling and conversion can be found in the value RAM and are available at any time.