MPC8377ECVRAGDA datasheet(46/124 Pages) FREESCALE

46 / 124 page

MPC8377E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

Enhanced Secure Digital Host Controller (eSDHC)

This means that clock can be delayed versus data up to 15 ns (external delay line) in ideal case of

tSFSCLKL =20 ns:

tCLK_DELAY + 5 – 0 < 20 + tDATA_DELAY

tCLK_DELAY < 15 + tDATA_DELAY

11.2.1.3

Full-Speed Write Combined Formula

The following equation is the combined formula to calculate the allowed skew range between the

SD_CLK and SD_DAT/CMD signals on the PCB.

tCLK_DELAY + tIH – tSFSKHOX < tSFSCKL + tDATA_DELAY < tSFSCK+ tCLK_DELAY – tISU – tSFSKHOV

11.2.2

Full-Speed Input Path (Read)

Figure 28 provides the data and command input timing diagram.

Figure 28. Full Speed Input Path

11.2.2.1

Full-Speed Read Meeting Setup (Maximum Delay)

The following equations show how to calculate the allowed combined propagation delay range of the

SD_CLK and SD_DAT/CMD signals on the PCB.

tCLK_DELAY + tDATA_DELAY + tODLY + tSFSIVKH < tSFSCK

tCLK_DELAY + tDATA_DELAY < tSFSCK – tODLY – tSFSIVKH – tINT_CLK_DLY

11.2.2.2

Full-Speed Read Meeting Hold (Minimum Delay)

There is no minimum delay constraint due to the full clock cycle between the driving and sampling of data.

tCLK_DELAY + tOH + tDATA_DELAY > tSFSIXKH

tCLK_DELAY

Output from the

SD CLK at

the Card Pin

SD Card Pins

tSFSIVKH

tSFSIXKH

Driving

Edge

Sampling

Edge

tOH

tDATA_DELAY

tODLY

tSFSCK (Clock Cycle)

(MPC8377E Input Hold)

SD CLK at the

MPC8377E Pin

Input at the

MPC8377E Pins

MPC8377ECVRAGDA Scheda tecnica(PDF) 46 Page - Freescale Semiconductor, Inc

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