MPC8377ECVRAGDA datasheet(76/124 Pages) FREESCALE

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MPC8377E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

High-Speed Serial Interfaces (HSSI)

Figure 49 shows the SPI timing in slave mode (external clock).

Figure 49. SPI AC Timing in Slave Mode (External Clock) Diagram

Figure 50 shows the SPI timing in master mode (internal clock).

Figure 50. SPI AC Timing in Master Mode (Internal Clock) Diagram

21 High-Speed Serial Interfaces (HSSI)

The MPC8377E features two serializer/deserializer (SerDes) interfaces to be used for high-speed serial

interconnect applications. See Table 1 for the interfaces supported.

This section describes the common portion of SerDes DC electrical specifications, which is the DC

requirement for SerDes reference clocks. The SerDes data lane’s transmitter and receiver reference circuits

are also shown.

21.1

Signal Terms Definition

The SerDes utilizes differential signaling to transfer data across the serial link. This section defines terms

used in the description and specification of differential signals.

Figure 51 shows how the signals are defined. For illustration purpose, only one SerDes lane is used for

description. The figure shows waveform for either a transmitter output (SDn_TX and SDn_TX) or a

receiver input (SDn_RX and SDn_RX). Each signal swings between A volts and B volts where A > B.

SPICLK (input)

tNEIXKH

tNEIVKH

tNEKHOV

Input Signals:

SPIMOSI

(See Note)

Output Signals:

SPIMISO

(See Note)

Note: The clock edge is selectable on SPI.

SPICLK (output)

tNIIXKH

tNIKHOV

Input Signals:

SPIMISO

(See Note)

Output Signals:

SPIMOSI

(See Note)

Note: The clock edge is selectable on SPI.

tNIIVKH

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