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MPC8377ECVRAGDA Scheda tecnica(PDF) 70 Page - Freescale Semiconductor, Inc |
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MPC8377ECVRAGDA Scheda tecnica(HTML) 70 Page - Freescale Semiconductor, Inc |
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70 / 124 page  MPC8377E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2 70 Freescale Semiconductor Serial ATA (SATA) 16.3 Differential Receiver (Rx) Input Characteristics This section discusses the Gen1i/1.5G and Gen2i/3G differential receiver input AC characteristics. 16.3.1 Gen1i/1.5G Receiver Specifications Table 58 provides the Gen1i or 1.5 Gbits/s differential receiver input DC characteristics for the SATA interface. Table 59 provides the Gen1i or 1.5 Gbits/s differential receiver input AC characteristics for the SATA interface. Total jitter fC3dB =fBAUD/1667 USATA_TXTJfB/1667 — — 0.55 UIp-p 1 Deterministic jitter fC3dB =fBAUD/10 USATA_TXDJfB/10 — — 0.17 UIp-p 1 Deterministic jitter fC3dB =fBAUD/500 USATA_TXDJfB/500 — — 0.19 UIp-p 1 Deterministic jitter fC3dB =fBAUD/1667 USATA_TXDJfB/1667 — — 0.35 UIp-p 1 Note: 1 Measured at Tx output pins peak to peak phase variation, random data pattern. Table 58. Gen1i/1.5G Receiver Input DC Specifications Parameter Symbol Min Typical Max Units Notes Differential input voltage VSATA_RXDIFF 240 500 600 mVp-p 1 Differential Rx input impedance ZSATA_RXSEIM 85 100 115 Ω — Note: 1 Voltage relative to common of either signal comprising a differential pair. Table 59. Gen 1i/1.5G Receiver AC Specifications Parameter Symbol Min Typical Max Units Notes Unit interval TUI 666.4333 666.667 670.2333 ps — Total jitter, data-data 5UI USATA_TXTJ5UI — — 0.43 UIp-p 1 Total jitter, data-data 250 UI USATA_TXTJ250UI — — 0.60 UIp-p 1 Deterministic jitter, data-data 5UI USATA_TXDJ5UI — — 0.25 UIp-p 1 Table 57. Gen 2i/3G Transmitter AC Specifications (continued) Parameter Symbol Min Typical Max Units Notes |
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