ATmega162V-8AI datasheet(91/324 Pages) ATMEL

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2513K–AVR–07/09

ATmega162/V

Counter Unit

The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure

34 shows a block diagram of the counter and its surroundings.

Figure 34. Counter Unit Block Diagram

Signal description (internal signals):

count

Increment or decrement TCNT0 by 1.

direction

Select between increment and decrement.

clear

Clear TCNT0 (set all bits to zero).

clk

Timer/Counter clock, referred to as clk

T0 in the following.

top

Signalize that TCNT0 has reached maximum value.

bottom

Signalize that TCNT0 has reached minimum value (zero).

Depending of the mode of operation used, the counter is cleared, incremented, or decremented

at each timer clock (clk

T0). clkT0 can be generated from an external or internal clock source,

selected by the clock select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the

timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of

whether clk

T0 is present or not. A CPU write overrides (has priority over) all counter clear or

count operations.

The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in

the Timer/Counter Control Register (TCCR0). There are close connections between how the

counter behaves (counts) and how waveforms are generated on the output Compare Output

OC0. For more details about advanced counting sequences and waveform generation, see

“Modes of Operation” on page 94.

The Timer/Counter Overflow (TOV0) Flag is set according to the mode of operation selected by

the WGM01:0 bits. TOV0 can be used for generating a CPU interrupt.

Output Compare

Unit

The 8-bit comparator continuously compares TCNT0 with the Output Compare Register

(OCR0). Whenever TCNT0 equals OCR0, the comparator signals a match. A match will set the

Output Compare Flag (OCF0) at the next timer clock cycle. If enabled (OCIE0 = 1 and Global

Interrupt Flag in SREG is set), the Output Compare Flag generates an output compare interrupt.

The OCF0 Flag is automatically cleared when the interrupt is executed. Alternatively, the OCF0

Flag can be cleared by software by writing a logical one to its I/O bit location. The waveform gen-

erator uses the match signal to generate an output according to operating mode set by the

WGM01:0 bits and Compare Output mode (COM01:0) bits. The max and bottom signals are

used by the waveform generator for handling the special cases of the extreme values in some

modes of operation (See “Modes of Operation” on page 94.).

Figure 35 shows a block diagram of the output compare unit.

DATA BUS

TCNTn

Control Logic

count

TOVn

(Int.Req.)

Clock Select

top

Edge

Detector

( From Prescaler )

clk

bottom

direction

clear

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