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ATmega162V-8AI Scheda tecnica(PDF) 43 Page - ATMEL Corporation |
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ATmega162V-8AI Scheda tecnica(HTML) 43 Page - ATMEL Corporation |
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43 / 324 page ![]() 43 2513K–AVR–07/09 ATmega162/V Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consump- tion to the application’s requirements. To enter any of the five sleep modes, the SE bit in MCUCR must be written to logic one and a SLEEP instruction must be executed. The SM2 bit in MCUCSR, the SM1 bit in MCUCR, and the SM0 bit in the EMCUCR Register select which sleep mode (Idle, Power-down, Power-save, Standby, or Extended Standby) will be activated by the SLEEP instruction. See Table 16 for a summary. If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for four cycles in addition to the start-up time, executes the interrupt rou- tine, and resumes execution from the instruction following SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes up from sleep. If a Reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector. Figure 18 on page 35 presents the different clock systems in the ATmega162, and their distribu- tion. The figure is helpful in selecting an appropriate sleep mode. MCU Control Register – MCUCR • Bit 5 – SE: Sleep Enable The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately after waking up. • Bit 4 – SM1: Sleep Mode Select Bit 1 The Sleep Mode Select bits select between the five available sleep modes as shown in Table 16. MCU Control and Status Register – MCUCSR • Bit 5 – SM2: Sleep Mode Select Bit 2 The Sleep Mode Select bits select between the five available sleep modes as shown in Table 16. Bit 765 4321 0 SRE SRW10 SE SM1 ISC11 ISC10 ISC01 ISC00 MCUCR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 000 0000 0 Bit 765 4321 0 JTD –SM2 JTRF WDRF BORF EXTRF PORF MCUCSR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 000 0000 0 |
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