ATmega162V-8AI datasheet(44/324 Pages) ATMEL

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2513K–AVR–07/09

ATmega162/V

Extended MCU

Control Register –

EMCUCR

• Bit 7 – SM0: Sleep Mode Select Bit 0

The Sleep Mode Select bits select between the five available sleep modes as shown in Table

16.

Note:

1. Standby mode and Extended Standby mode are only available with external crystals or

resonators.

Idle Mode

When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle

mode, stopping the CPU but allowing the SPI, USART, Analog Comparator, Timer/Counters,

Watchdog, and the interrupt system to continue operating. This sleep mode basically halts

clk

CPU and clkFLASH, while allowing the other clocks to run.

Idle mode enables the MCU to wake up from external triggered interrupts as well as internal

ones like the Timer Overflow and USART Transmit Complete interrupts. If wake-up from the

Analog Comparator interrupt is not required, the Analog Comparator can be powered down by

setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will

reduce power consumption in Idle mode.

Power-down Mode

When the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter Power-

down mode. In this mode, the external Oscillator is stopped, while the external interrupts and the

Watchdog continue operating (if enabled). Only an External Reset, a Watchdog Reset, a Brown-

out Reset, an External Level Interrupt on INT0 or INT1, an external interrupt on INT2, or a pin

change interrupt can wake up the MCU. This sleep mode basically halts all generated clocks,

allowing operation of asynchronous modules only.

Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed

level must be held for some time to wake up the MCU. Refer to “External Interrupts” on page 84

for details.

When waking up from Power-down mode, there is a delay from the wake-up condition occurs

until the wake-up becomes effective. This allows the clock to restart and become stable after

having been stopped. The wake-up period is defined by the same CKSEL Fuses that define the

Reset Time-out period, as described in “Clock Sources” on page 36.

Bit

765

4321

SM0

SRL2

SRL1

SRL0

SRW01

SRW00

SRW11

ISC2

EMCUCR

Read/Write

R/W

Initial Value

000

0000

Table 16. Sleep Mode Select

SM2

SM1

SM0

Sleep Mode

000

Idle

001

Reserved

010

Power-down

011

Power-save

100

Reserved

101

Reserved

110

Standby(1)

Extended Standby(1)

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