CDCE72010RGCT datasheet(46/73 Pages) TI

46 / 73 page

CDCE72010

SCAS858A – JUNE 2008 – REVISED JULY 2009.............................................................................................................................................................. www.ti.com

SPI

RAM

POWER UP

BIT NAME

DESCRIPTION/FUNCTION

BIT

BLOCK

CONDITION

Address 0

Address 1

Address 2

Address 3

Reference Divider M bit 0

Reference Divider M bit 1

Reference Divider M bit 2

Reference Divider M bit 3

Reference Divider M bit 4

Reference Divider M bit 5

Reference

Reference Divider M bit 6

(PRI/SEC)

EEPROM

Reference Divider M bit 7

Divider M

Reference Divider M bit 8

Reference Divider M bit 9

M10

Reference Divider M bit 10

M11

Reference Divider M bit 11

M12

Reference Divider M bit 12

M13

Reference Divider M bit 13

VCXO Divider N bit 0

VCXO Divider N bit 1

VCXO Divider N bit 2

VCXO Divider N bit 3

VCXO Divider N bit 4

VCXO Divider N Bit 5

VCXO Divider N Bit 6

VCXO/AUX/SEC

EEPROM

Divider N

VCXO Divider N Bit 7

VCXO Divider N Bit 8

VCXO Divider N Bit 9

N10

VCXO Divider N Bit 10

N11

VCXO Divider N Bit 11

N12

VCXO Divider N Bit 12

N13

VCXO Divider N Bit 13

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