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CDCE72010RGCT Scheda tecnica(PDF) 60 Page - Texas Instruments

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Il numero della parte CDCE72010RGCT
Spiegazioni elettronici  Ten Output High Performance Clock Synchronizer, Jitter Cleaner, and Clock Distributor
PDF  73 Pages
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Produttore elettronici  TI [Texas Instruments]
Homepage  http://www.ti.com
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CDCE72010RGCT Scheda tecnica(HTML) 60 Page - Texas Instruments

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DEVICE LAYOUT
Onlyonesideofthepinpadsisshown.
Onlytwocapacitorsareillustrated.
TopSideThermalPADLayout
BottomSideThermalPADLayout
Onlytwocapacitorsareillustrated.
CDCE72010
SCAS858A – JUNE 2008 – REVISED JULY 2009.............................................................................................................................................................. www.ti.com
The CDCE72010 is a high performance device packaged in a QFN-64. The die has all the ground pins bounded
to the thermal PAD on the bottom of the package. Therefore it is essential that the connection from the thermal
PAD to the ground layers should be low impedance. In addition, the thermal path in a QFN package is via the
thermal PAD on the bottom of the package. Therefore, the layout of the PAD is very important and it will affect
the thermal performance as well as the overall performance of the device. The illustration shown provides
optimal performance in terms of thermal issues, inductance and power supply bypassing. The 10 X 10 Filled VIA
pattern recommended allows for a low inductance connection between the thermal ground pad and the ground
plane of the board. This pattern forms a low thermal resistive path for the heat generated by the die to get
dissipated through the ground plane and to the exposed bottom side ground pad. It is recommended that solder
mask not be used on this bottom side pad to maximize its effectiveness as a thermal heat sink. The
recommended layout drives the thermal conductivity to 22.8 C/W in still air and 13.8 C/W in a 100LFM air flow if
implemented on a JEDEC compliant test thermal board.
Figure 26. Device Layout
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