CDCE72010RGCT datasheet(56/73 Pages) TI

Il numero della parte	CDCE72010RGCT

Spiegazioni elettronici	Ten Output High Performance Clock Synchronizer, Jitter Cleaner, and Clock Distributor

PDF	73 Pages

Scroll/Zoom	100%

Produttore elettronici	TI [Texas Instruments]

Homepage	http://www.ti.com

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56 / 73 page

DIGITAL LOCK DETECT

Power_Down

Lock_Out

Lock_In

160kW

5pF

PLL_LOCK

Output

=0.6V

high

=0.4V

low

Lock

DigitalLockDetection

Out-of-Lock

Out

CDCE72010

SCAS858A – JUNE 2008 – REVISED JULY 2009.............................................................................................................................................................. www.ti.com

Table 15. Number of Successive Lock Events Inside the Lock Detect Window

(Register 7 RAM Bits [4:3]) the PLL Lock Signal is Delayed for Number of

FB_CLK Events

NO. OF SUCCESSIVE LOCK

LOCKC1

LOCKC0

EVENTS

64(1)

256

(1)

Default

When selecting the digital PLL lock option, PLL_LOCK will possibly jitter several times between lock and out of

lock until a stable lock is detected. A single “low-to-high” step can be reached with a wide lock detect window

and high number of successive clock cycles. PLL_LOCK will return to out of lock if just one cycle is outside the

lock detect window.

Figure 22. Digital Lock

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