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CDCE72010RGCT Scheda tecnica(PDF) 17 Page - Texas Instruments |
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CDCE72010RGCT Scheda tecnica(HTML) 17 Page - Texas Instruments |
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17 / 73 page  APPLICATION INFORMATION PHASE NOISE ANALYSIS CDCE72010 www.ti.com.............................................................................................................................................................. SCAS858A – JUNE 2008 – REVISED JULY 2009 Phase noise is measured in a closed loop mode of 491.52MHz VCXO and 30.72MHz reference and a 100Hz loop. Output 1 is measured for divide by one, output 6 for divide by 4, and output 9 for divide by 16. Table 1. Phase Noise for LVPECL High Swing Phase Noise Specifications under following configuration: VCXO = 491.52MHz, REF = 30.72MHz, Divide by = 491.52MHz, Divide by 4 = 122.88MHz, Divide by 16 = 30.72MHz, PFD Frequency = 240KHz, Charge Pump Current = 2mA, Loop BW = 100Hz, Output 1 = 491.52 MHZ, Output Buffer: LVPECL-HS PHASE NOISE VCXO OPEN REFERENCE LVPECL-HS LVPECL-HS LVPECL-HS UNIT AT OFFSET LOOP 30.72MHz DIVIDE BY 1 DIVIDE BY 4 DIVIDE BY 16 10Hz –64 –107 –80 –92 –105 dBc/Hz 100Hz –99 –123 –92 –104 –116 dBc/Hz 1kHz –113 –134 –115 –127 –139 dBc/Hz 10kHz –135 –153 –135 –145 –158 dBc/Hz 100kHz –148 –156 –146 –155 –162 dBc/Hz 1MHz –148 –158 –146 –155 –162 dBc/Hz 10MHz –149 –147 –156 dBc/Hz Table 2. Phase Noise for LVDS High Swing Phase Noise Specifications under following configuration: VCXO = 491.52MHz, REF = 30.72MHz, Divide by = 491.52MHz, Divide by 4 = 122.88MHz, DIvide by 16 = 30.72MHz, PFD Frequency = 240KHz, Charge Pump Current = 2mA Loop BW = 100Hz, Output 1 = 491.52 MHZ, Output Buffer: LVDS-HS VCXO OPEN LVDS–HS LVDS-HS LVDS-HS PARAMETER REFERENCE UNIT LOOP DIVIDE BY 1 DIVIDE BY 4 DIVIDE BY 16 10Hz –64 –107 –82 –94 –104 dBc/Hz 100Hz –99 –123 –92 –105 –117 dBc/Hz 1kHz –113 –134 –114 –127 –139 dBc/Hz 10kHz –135 –153 –135 –145 –151 dBc/Hz 100kHz –148 –156 –145 –152 –153 dBc/Hz 1MHz –148 –158 –146 –152 –153 dBc/Hz 10MHz –149 –146 –152 dBc/Hz Table 3. Phase Noise for LVCMOS Phase Noise Specifications under following configuration: VCXO = 491.52MHz, REF = 30.72MHz, Divide by = 491.52MHz, Divide by 4 = 122.88MHz, DIvide by 16 = 30.72MHz, PFD Frequency = 240KHz, Charge Pump Current = 2mA, Loop BW = 100Hz, Output 1 = 491.52 MHZ, Output Buffer: LVCMOS VCXO OPEN LVCMOS LVCMOS PARAMETER REFERENCE N/A UNIT LOOP DIVIDE BY 4 DIVIDE BY 16 10Hz –64 –107 –91 –105 dBc/Hz 100Hz –99 –123 –104 –116 dBc/Hz 1kHz –113 –134 –127 –139 dBc/Hz 10kHz –135 –153 –140 –151 dBc/Hz 100kHz –148 –156 –151 –159 dBc/Hz 1MHz –148 –158 –153 –160 dBc/Hz 10MHz –149 –154 dBc/Hz Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 17 Product Folder Link(s): CDCE72010 |
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