MPC5125 datasheet(53/92 Pages) FREESCALE

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Electrical and Thermal Characteristics

MPC5125 Microcontroller Data Sheet, Rev. 3

Freescale Semiconductor

4.3.5.4

SDR SDRAM AC Timing Specifications

NOTE

To achieve better timing, balance the loading of DQS as MCK although DQS is not used in

SDR mode.

Figure 9 shows the DDR SDRAM write timing.

Figure 9. DDR Write Timing

NOTES:

1 Measured with clock pin loaded with differential 100

Ω termination resistor.

2 Measured with all outputs except the clock loaded with 50

Ω termination resistor to V

DD_IO_MEM/2.

3 All transitions measured at mid-supply (V

DD_IO_MEM/2).

4 In this window, the first rising edge of DQS should occur. From the start of the window to DQS rising edge, DQS should be low.

5 The window position is given for t

DQSEN = 2.5 tCK (RDLY = 2, HALF DQS DLY = 1, QUART DQS DLY = 0) with CL = 3 DDR2

SDRAM device. For other values of tDQSEN, the window position is shifted accordingly.

Table 24. SDR SDRAM Timing Specifications

At recommended operating conditions with VDD_IO_MEM of ±5%

Parameter

Symbol

Min

Max

Unit Notes SpecID

Clock cycle time, CL = x

tCK

7500

—

A5.1

CK HIGH pulse width

tCH

0.43

0.57

tCK

1,3

NOTES:

1 Measured with clock pin loaded with 50

Ω termination resistor to mid-supply.

A5.3

CK LOW pulse width

tCL

0.43

0.57

tCK

1,3

A5.4

Address, control, and data output setup time relative

to MCK rising edge

tOS(base)

tCK/2 – 1000

—

2,3

2 Measured with all outputs except the clock loaded with 50

Ω termination resistor to V

DD_IO_MEM/2.

3 All transitions measured at mid-supply (V

DD_IO_MEM/2).

A5.6

Address, control, and data output hold time relative to

MCK rising edge

tOH(base)

tCK/2 – 1000

—

2,3

A5.7

Input data set-up time, relative to MCK

tIS

1000

—

A5.15

Input data hold time, relative to MCK

tIH

1000

—

A5.16

MCK

tCH

tCL

DQS

tDQSS

DQ, DM(out)

tDS

tDH

tCK

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