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MPC5125 Scheda tecnica(PDF) 78 Page - Freescale Semiconductor, Inc |
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MPC5125 Scheda tecnica(HTML) 78 Page - Freescale Semiconductor, Inc |
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78 / 92 page ![]() MPC5125 Microcontroller Data Sheet, Rev. 3 Electrical and Thermal Characteristics Freescale Semiconductor 78 Figure 43. Timing Diagram — SPI Master Mode, Format 1 (CPHA = 1) Table 45. Timing Specifications — SPI Slave Mode, Format 1 (CPHA = 1) 1 NOTES: 1 Output timing is specified at a nominal 50 pF load. Sym Description Min Max Units SpecID 1 SCK cycle time, programmable in the PSC CCS register 30.0 — ns A20.56 2 SCK pulse width, 50% SCK duty cycle 15.0 — ns A20.57 3 Slave select clock delay 0.0 — ns A20.58 4 Output data valid — 14.0 ns A20.59 5 Input data setup time 2.0 — ns A20.60 6 Input data hold time 1.0 — ns A20.61 7 Slave disable lag time 0.0 — ns A20.62 8 Minimum sequential transfer delay = 2 × IP bus clock cycle time 30.0 — ns A20.63 SCK (CLKPOL=0) SCK (CLKPOL=1) MOSI Output Output Output SS Output MISO Input 1 22 7 8 3 4 6 10 9 9 10 5 |
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