6402 datasheet(7/250 Pages) INTEL

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Intel® 6400/6402 Advanced Memory Buffer Datasheet

14.6.3 Firmware Support Registers................................................................... 221

14.7 DFX Registers (Function 5) ............................................................................... 222

14.7.1 Transparent Mode Registers................................................................... 222

14.7.2 Logic Analyzer Interface (LAI) Registers .................................................. 223

14.7.3 Error Injection Registers........................................................................ 230

14.8 Bring-up and Debug Registers (Function 6)......................................................... 231

14.8.1 SPAD[1:0]: Scratch Pad ........................................................................ 231

14.8.2 Southbound FBD Intel® Interconnect BIST Registers................................. 231

14.8.3 Northbound FBD Intel IBIST Registers..................................................... 236

SPD Bits ................................................................................................................ 243

15.1 Access Mechanisms ......................................................................................... 243

15.1.1 Raw Cards A, B, and C .......................................................................... 243

15.1.2 Raw Cards D, E, H, and J....................................................................... 244

15.1.3 Category Byte 99 ................................................................................. 245

Glossary ................................................................................................................ 247

A.1

Terms and Definitions ...................................................................................... 247

Figures

1-1

Advanced Memory Buffer Block Diagram............................................................... 13

1-2

AMB Interfaces ................................................................................................. 14

2-1

Delays Through an AMB ..................................................................................... 22

2-2

Command to Data Delay Timing .......................................................................... 23

3-1

Nominal Turnaround Time Timing Diagram ........................................................... 31

4-1

Latency Timing Diagrams ................................................................................... 44

4-2

tDVA and tDVB Timing Diagram .......................................................................... 46

4-3

tjit and tjitHP Timing Diagram ............................................................................. 47

4-4

tCVA and tCVB Timing Diagram........................................................................... 47

4-5

tECVA and tECVB Timing Diagram ....................................................................... 47

4-6

TDQSCK Timing Diagram.................................................................................... 48

4-7

DQ and CB (ECC) Setup/Hold Relationship to/from DQS Timing Diagram .................. 48

4-8

Write Preamble Duration Timing Diagram ............................................................. 49

4-9

Write Postamble Duration Timing Diagram ............................................................ 49

5-1

AMB LAI Mode Usage Diagram ............................................................................ 54

5-2

AMB LAI Mode Connectivity ................................................................................ 55

5-3

LAI Signal Group Timing..................................................................................... 60

5-4

LAI Match and Mask Logic .................................................................................. 61

5-5

Local Event Mux Block Diagram........................................................................... 62

5-6

EVBus Overview................................................................................................ 64

5-7

Event Bus Signal Timing..................................................................................... 65

5-8

LAI Qualification Signal Block Diagram ................................................................. 66

5-9

Block Diagram of AMB in LAI Mode ...................................................................... 67

7-1

SMBus Configuration Read (Block Write / Block Read, PEC Enabled) ......................... 79

7-2

SMBus Configuration Read (Write Bytes / Read Bytes, PEC Enabled) ........................ 80

7-3

SMBus Configuration Double Word Write (Block Write, PEC Enabled) ........................ 80

7-4

SMBus Configuration Double Word Write (Write Bytes, PEC Enabled)........................ 81

7-5

SMBus Configuration Word Write (Block Write, PEC Disabled).................................. 81

7-6

SMBus Configuration Byte Write (Write Bytes, PEC Disabled)................................... 81

8-1

AMB Clock Domains ........................................................................................... 84

8-2

FBD PLL Power Supply Filter ............................................................................... 89

9-1

Cold Power-Up Reset ......................................................................................... 96

9-2

AMB Fast Reset Sequence .................................................................................. 96

10-1 DRAM Architecture ............................................................................................ 99

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