6402 datasheet(4/250 Pages) INTEL

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Intel® 6400/6402 Advanced Memory Buffer Datasheet

4.1.1

Absolute Maximum Ratings ......................................................................37

4.1.2

Operating DC Parameters ........................................................................37

4.1.3

AMB Power Specifications ........................................................................38

4.2

FB-DIMM Electrical Timing Specifications...............................................................44

4.3

DDR2 DRAM Interface Electrical Specifications .......................................................45

4.4

DDR2 Electrical Output Timing Specifications .........................................................46

4.4.1

Description of DQ/DQS Alignment .............................................................46

4.4.2

Description of ADD/CMD/CNTL Outputs......................................................46

4.4.3

Test Load Specification ............................................................................46

4.4.4

tDVA and tDVB Parameter Description .......................................................46

4.4.5

tjit and tjitHP Parameter Description..........................................................46

4.4.6

tCVA, tCVB, tECVA and tECVB Parameter Description...................................47

4.4.7

tDQSCK Timing Parameter Description.......................................................47

4.4.8

DQ and CB (ECC) Setup/Hold Relationships to/from DQS

(Read Operation)....................................................................................48

4.4.9

Write Preamble Duration..........................................................................49

4.4.10 Write Postamble Duration ........................................................................49

4.4.11 Advance Memory Buffer Component Electrical Timing Summary ....................50

4.4.12 Reference DDR2 Interface Package Trace Lengths .......................................51

4.5

SMBUS Interface ...............................................................................................51

4.6

Miscellaneous I/O (1.5 Volt CMOS Driver) .............................................................51

4.7

Thermal Diode and Analog to Digital Converter (ADC).............................................51

4.7.1

Thermal Sensor Effects on the AMB’s

Functional Behavior.................................................................................52

Debug and Logic Analyzer Mode...............................................................................53

5.1

Logic Analyzer Interface (LAI) Mode .....................................................................53

5.1.1

LAI Mode Architecture .............................................................................54

5.1.2

LAI Mode Clocking ..................................................................................55

5.1.3

LAI Mode Pins ........................................................................................55

5.1.4

LAI Mode Signal Definitions ......................................................................56

5.1.5

LAI to DDR Pin Mapping...........................................................................57

5.1.6

FBD to LAI Signal Mapping .......................................................................58

5.1.7

LAI to DDR Pin Timing .............................................................................59

5.1.8

LAI Features ..........................................................................................60

5.1.9

LAI Block Diagram ..................................................................................67

5.2

Normal Mode Debug Features..............................................................................68

5.2.1

Normal Mode Debug Triggers ...................................................................68

5.2.2

Error Injection........................................................................................68

6Errors ......................................................................................................................71

6.1

Types of Errors and Responses ............................................................................71

6.1.1

FBD Link Errors ......................................................................................71

6.1.2

DDR Errors ............................................................................................73

6.1.3

Host Protocol Errors ................................................................................73

6.1.4

Other Errors...........................................................................................74

6.2

Error Logging ....................................................................................................74

6.2.1

Error Logging Procedure ..........................................................................74

6.3

Fail Over Mode Support ......................................................................................75

6.4

Failback to Pass-Thru .........................................................................................75

7SMBus Interface ......................................................................................................77

7.1

System Management Access ...............................................................................77

7.1.1

SMBus 2.0 Specification Compatibility........................................................77

7.1.2

Supported SMBus Commands...................................................................77

7.1.3

FBD AMB Register Access Protocols ...........................................................78

7.1.4

SMBus Error Handling..............................................................................81

7.1.5

SMBus Resets ........................................................................................81

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