6402 datasheet(59/250 Pages) INTEL

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Intel® 6400/6402 Advanced Memory Buffer Datasheet

Debug and Logic Analyzer Mode

Output to logic analyzer is lane by lane

early data

[lane 9][lane 1][lane0]

[FE20,FE21,….,aE0] ……… [bC5, bC4, aC7, aC6, aC5, aC4] [bC1, bC0, aC3, aC2, aC1,

aC0]

late data

[lane 9][lane 1][lane0]

[FE14,FE15,….,FE19] … … [cC7, cC6, cC5, cC4, bC7, bC6] [cC3,cC2, cC1, cC0, bC3,

bC2]

Note:

CRC codes in A cmd (aE0 - aE13) are a function of FE21:FE14 of previous frame.

5.1.7

LAI to DDR Pin Timing

The phases of data presented to the logic analyzer have some odd timing due to reuse

of some many different types of DDR I/O outputs to achieve the desired pin count. The

LA will compensate for these predictable phase offsets.

Table 5-5.

Typical FBD Southbound Command Frame

Transfer \ Bit

987

65432

N 0

aE0

aE7

aE8

F0=0

aC20

aC16

aC12

aC8

aC4

aC0

N 1

aE1

aE6

aE9

F1=0

aC21

aC17

aC13

aC9

aC5

aC1

N 2

aE2

aE5

aE10

aE13

aC22

aC18

aC14

aC10

aC6

aC2

N 3

aE3

aE4

aE11

aE12

aC23

aC19

aC15

aC11

aC7

aC3

N 4

FE21

000

bC20

bC16

bC12

bC8

bC4

bC0

N 5

FE20

000

bC21

bC17

bC13

bC9

bC5

bC1

N 6

FE19

000

bC22

bC18

bC14

bC10

bC6

bC2

N 7

FE18

000

bC23

bC19

bC15

bC11

bC7

bC3

N 8

FE17

000

cC20

cC16

cC12

cC8

cC4

cC0

N 9

FE16

000

cC21

cC17

cC13

cC9

cC5

cC1

N 10

FE15

000

cC22

cC18

cC14

cC10

cC6

cC2

N 11

FE14

000

cC23

cC19

cC15

cC11

cC7

cC3

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