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6402 Scheda tecnica(PDF) 80 Page - Intel Corporation |
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6402 Scheda tecnica(HTML) 80 Page - Intel Corporation |
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80 / 250 page ![]() SMBus Interface 80 Intel® 6400/6402 Advanced Memory Buffer Datasheet 7.1.3.2 Configuration Register Write Protocol Configuration writes are accomplished through a series of SMBus writes. As with configuration reads, a write sequence is first used to initialize the Bus Number, Device, Function, and Register Number for the configuration access. The writing of this information can be accomplished through any combination of the supported SMBus write commands (Block, Word or Byte). On SMBus, there is no concept of byte enables. Therefore, the Register Number written to the slave is assumed to be aligned to the length of the Internal Command. In other words, for a Write Byte internal command, the Register Number specifies the byte address. For a Write DWord internal command, the two least-significant bits of the Register Number are ignored. This is different from PCI where the byte enables are used to indicate the byte of interest. After all the information is set up, the SMBus master initiates one or more writes which sets up the data to be written. The final write (End bit is set) initiates an internal configuration write. If an error occurred, the SMBus interface NACKs the last write operation just before the stop bit. Examples of configuration writes are illustrated below. For the definition of the diagram conventions below, refer to the SMBus Specification, Rev. 2.0. Figure 7-2. SMBus Configuration Read (Write Bytes / Read Bytes, PEC Enabled) S X011_XXX W A Cmd = 10010000 A Reserved A PEC A P S X011_XXX W A Cmd = 00010000 A Device/Function A PEC A P S X011_XXX W A Cmd = 01010000 A Register[7:0] A PEC S X011_XXX W A Cmd = 00010000 Sr X011_XXX R A Data[31:24] S X011_XXX W A Cmd = 00010000 A Sr X011_XXX R A Data[23:16] A PEC N P S X011_XXX W A Cmd = 00010000 A Sr X011_XXX R A Data[15:8] A PEC N P S X011_XXX W A Cmd = 01010000 A Sr X011_XXX R A Data[7:0] A PEC N P A A P A PEC N P S X011_XXX W A Cmd = 10010000 Sr X011_XXX R A Status A A PEC N P S X011_XXX W A Cmd = 00010000 A Register[15:8] A PEC A P Figure 7-3. SMBus Configuration Double Word Write (Block Write, PEC Enabled) A S X011_XXX WA Cmd = 11011110 A Byte Count =8 A Reserved A Device/Function A Reg Number[15:8] A Reg Number [7:0] A Data[31:24] Data[23:16] A Data[16:8] A Data[7:0] A PEC A P |
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