6402 datasheet(184/250 Pages) INTEL

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Registers

184

Intel® 6400/6402 Advanced Memory Buffer Datasheet

• Internal clock domain phase offsets

14.3.4.1

PERSBYTE[13:0]NXT: Personality Bytes

These bytes are loaded from SPD bytes 114:101 respectively.

(PERSBYTE13NXT = SPD byte 114, ... , PERSBYTE0NXT = SPD byte 101)

14.3.4.2

PERSBYTE[13:0]CUR: Personality Bytes

14.3.5

Hardware Configuration Registers

14.3.5.1

CMD2DATANXT: Next Value of Command to Data Delay

This register has the next value of the command to data delay. This will be used after

the next fast reset. For correct DIMM operation, CMD2DATA may be limited to a subset

of the architecturally valid values. The allowed values are AMB specific and may vary

with frequency. Values come from SPD.

Function: 1

Offset:

BDh:B0h

Bit

Attr

Default

Description

7:0

RWST

PData: Personality Data Byte

Implementation specific registers

Function: 1

Offset:

BDh:B0h

Bit

Attr

Default

Description

7:0

ROST

PData: Personality Data Byte

Implementation specific registers

Device:

NodeID

Function: 1

Offset:

E8h

Bit

Attr

Default

Description

7:4

RWST

DLYFRMS: Number of frames

This specifies full frame delay part of the command to data delay.

0 - 9: Valid delays

10 - 15: Reserved

3:0

RWST

DLYFRAC: Fractional delay of command to data

This specifies fractional frame delay part of the command to data delay.

0 - 11: Specifies the delay in 1UI increments

12 - 15: Reserved

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