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SSM2518CPZ-R7 Scheda tecnica(PDF) 44 Page - Analog Devices

Il numero della parte SSM2518CPZ-R7
Spiegazioni elettronici  Digital Input Stereo, 2 W, Class-D
PDF  48 Pages
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Produttore elettronici  AD [Analog Devices]
Homepage  http://www.analog.com
Logo AD - Analog Devices

SSM2518CPZ-R7 Scheda tecnica(HTML) 44 Page - Analog Devices

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SSM2518
Data Sheet
Rev. A | Page 44 of 48
DRC CONTROL 7 REGISTER
Address: 0x10, Reset: 0x26, Name: DRC_Control_7
Table 29. Bit Descriptions for DRC_Control_7
Bits
Bit Name
Settings
Description
Reset
Access
[7:4]
HDT_NOR
DRC Normal Operation Hold Time. Used to prevent the gain curve
calculation from increasing too quickly.
0x2
RW
0000
0 ms
0001
0.67 ms
0010
1.33 ms
0011
2.67 ms
0100
5.33 ms
0101
10.66 ms
0110
21.32 ms
0111
42.64 ms
1000
85.28 ms
1001
170.56 ms
1010
341.12 ms
1011
682.24 ms
1100
1.364 sec
1101
Reserved
1110
Reserved
1111
Reserved
[3:0]
HDT_NG
DRC Noise Gate Hold Time. Used to prevent the DRC from entering noise
gate too quickly.
0x6
RW
0000
0 ms
0001
0.67 ms
0010
1.33 ms
0011
2.67 ms
0100
5.33 ms
0101
10.66 ms
0110
21.32 ms
0111
42.64 ms
1000
85.28 ms
1001
170.56 ms



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